Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Kazuhisa Sunaga"'
Autor:
Shigeyuki Yanagimachi, Kazuhisa Sunaga
Publikováno v:
Journal of Japan Institute of Electronics Packaging. 14:532-536
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cb54977ff84c7f7689f58ca71b3d8e19
https://doi.org/10.5104/jiep.14.532
https://doi.org/10.5104/jiep.14.532
Autor:
Hideyuki Sugita, Tadahiro Kuroda, Masayuki Mizuno, Tsutomu Takeya, Kazuhisa Sunaga, Koichi Yamaguchi, Yoichi Yoshida
Publikováno v:
CICC
We present a 6Gb/s wireline receiver having Frequency Division Multiplexing (FDM) with four frequency sub-channels. Its 6GS/s discrete-time filter consumes less power than a conventional filter which requires the same number of high-speed analog mixe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2619e431e24c3cf3e47888076478e4e0
https://doi.org/10.1109/cicc.2010.5617600
https://doi.org/10.1109/cicc.2010.5617600
Publikováno v:
ISSCC
Much effort has been made toward producing a high-speed multi-tap decision feedback equalizer (DFE), which would be a key component in removing inter-symbol interference (ISI) in high-speed chip-to-chip communication. A loop-unrolled approach is wide
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::39960eb200766436b8c0cac493689471
https://doi.org/10.1109/isscc.2010.5434005
https://doi.org/10.1109/isscc.2010.5434005
Publikováno v:
ISSCC
With the demand for higher-speed inter-chip communication, DFEs have become increasingly more important. In a DFE, in order to cancel the first post-tap ISI, each decision data bit has to be fed back within 1T (1UI) and the second post-tap feedback w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d70e4d76e5564edcb711b10206d2a5f4
https://doi.org/10.1109/isscc.2009.4977414
https://doi.org/10.1109/isscc.2009.4977414
Autor:
M. Sugawara, Kouichi Yamaguchi, Makoto Takamiya, Kazuhisa Sunaga, Koichi Nose, Muneo Fukaishi, Yoshihiro Nakagawa, Takaaki Nedachi, Shunichi Kaeriyama
Publikováno v:
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
A backplane transceiver in 90 nm CMOS that employs duobinary signaling over copper traces is described. To introduce duobinary signaling into data transfers on printed boards, three techniques are developed: 1) edge equalization for equalizer adaptat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a532cff3a5107187ace11b790c791bce
https://doi.org/10.1109/isscc.2005.1493873
https://doi.org/10.1109/isscc.2005.1493873
Publikováno v:
ASP-DAC
A proposed linear regulator uses a flexible control technique of output current (FCOC) to achieve 96.5% efficiency. The FCOC technique drives a flexible output current according to the output current variation and stable output voltage supply. The li
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6f701c6d15c20a8e9c93c907fc859c63
https://doi.org/10.1109/aspdac.2001.913322
https://doi.org/10.1109/aspdac.2001.913322