Zobrazeno 1 - 10
of 29
pro vyhledávání: '"Kazimierz Krzywicki"'
Publikováno v:
Applied Sciences, Vol 14, Iss 7, p 2693 (2024)
Methods for reducing power consumption in circuits of finite state machines (FSMs) are discussed in this review. The review outlines the main approaches to solving this problem that have been developed over the last 40 years. The main sources of powe
Externí odkaz:
https://doaj.org/article/3de794f43c6244d9bc130e556f7b3687
Publikováno v:
Applied Sciences, Vol 13, Iss 18, p 10200 (2023)
This work proposes a method for hardware reduction in circuits of Mealy finite state machines (FSMs). The circuits are implemented as networks of interconnected look-up table (LUT) elements. The FSMs with twofold state assignment and encoding of outp
Externí odkaz:
https://doaj.org/article/6cbb8e7f60584ed0b5f715218f462082
Publikováno v:
Applied Sciences, Vol 12, Iss 16, p 8065 (2022)
The main contribution of this paper is a novel design method reducing the number of look-up table (LUT) elements in the circuits of three-block Mealy finite-state machines (FSMs). The proposed method is based on using codes of collections of outputs
Externí odkaz:
https://doaj.org/article/b4edec2ef5484df2a2faf21ca2420b55
Publikováno v:
Bulletin of the Polish Academy of Sciences: Technical Sciences, Vol 69, Iss 2 (2021)
Very often, a digital system includes sequential blocks which can be represented using a model of the finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and c
Externí odkaz:
https://doaj.org/article/54495ed035d44696aa030307d5788c6d
Publikováno v:
Energies, Vol 15, Iss 7, p 2636 (2022)
A method is proposed for optimizing circuits of sequential devices which are used in cyber-physical systems (CPSs) implemented using field programmable gate arrays (FPGAs). The optimizing hardware is a very important problem connected with implementi
Externí odkaz:
https://doaj.org/article/c49d9b0a2f094b9bbbc84a0ef230f49a
Publikováno v:
Applied Sciences, Vol 10, Iss 15, p 5115 (2020)
Very often, digital systems include sequential blocks which can be represented using a model of Mealy finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and p
Externí odkaz:
https://doaj.org/article/5903c2adfe63481cba32faaeaff20156
Publikováno v:
Applied Sciences, Vol 10, Iss 8, p 2762 (2020)
A method is proposed targeting implementation of FPGA-based Mealy finite state machines. The main goal of the method is a reduction for the number of look-up table (LUT) elements and their levels in FSM logic circuits. To do it, it is necessary to el
Externí odkaz:
https://doaj.org/article/309998afa4694474b0aae821a8fb63c1
Publikováno v:
Electronics
Volume 12
Issue 5
Pages: 1133
Volume 12
Issue 5
Pages: 1133
The main purpose of the method proposed in this article is to reduce the number of look-up-table (LUT) elements in logic circuits of sequential devices. The devices are represented by models of Mealy finite state machines (FSMs). Thesee are so-called
Publikováno v:
Electronics; Volume 11; Issue 19; Pages: 3089
A method is proposed which aims at reducing the numbers of look-up table (LUT) elements in logic circuits of Mealy finite state machines (FSMs). The FSMs with twofold state assignment are discussed. The reduction is achieved due to using two cores of
Publikováno v:
Electronics; Volume 11; Issue 13; Pages: 2050
A method is proposed which aims to reduce the hardware in FPGA-based circuits of Mealy finite state machines (FSMs). The proposed method is a type of structural decomposition method. Its main goal is the reducing the number of look-up table (LUT) ele