Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Kazi Fatima Sharif"'
Publikováno v:
Carpathian Journal of Electronic and Computer Engineering. 12:29-36
The fast evolution of battery functioned devices has caused approaches for decreasing power consumption in the memories is substantial. In this paper, a new proposal of SRAM with 8 transistors (8T) has been designed and also the cell itself is tested
Publikováno v:
International Journal of Reconfigurable and Embedded Systems (IJRES). 9:42
Area efficient and stable memory design is one of the most important tasks in designing system on chip. This research concentrates in designing a new type of hybrid memory model by using only nMOS transistors and memristor.The proposed memory cell is
Publikováno v:
2018 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE).
The high demand for memory devices by decreasing power consumption is significant. SRAM has been under its renewal phase by enduring the ever-increasing delay along with supporting low power applications. A New 10 transistor (lOT) SRAM cell architect
Autor:
Voicu Groza, Satyendra N. Biswas, Abdullah Al Mamun, Riazul Islam, Sunil R. Das, Kazi Fatima Sharif, Mansour H. Assaf, Md. Shah Miran
Publikováno v:
2017 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE).
Dynamic logic is highly in demand for designing low power VLSI circuits. It need less number of transistor though but the performance of the dynamic logic is not so promising due to prolonged contention time and higher leakage power. Present research
Publikováno v:
2017 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE).
This research proposed a new type of memory cell designed by using only nMOS transistors of 16nm, 22nm and 45nm (Arizona State University Predictive Technologies Model) PTM models and memristors. The memory cell consumes less power and also occupies
Publikováno v:
2017 International Conference on Innovative Mechanisms for Industry Applications (ICIMIA).
This research proposed a new design of memory cell of 7T SRAM using 16nm and 45nm (Arizona State University Predictive Technologies Model) PTM models. The memory cell provides larger static noise margin in hold state and a better read operation by co
Publikováno v:
2017 International Conference on Innovative Mechanisms for Industry Applications (ICIMIA).
Dynamic logic is most area effective technique for designing VLSI circuit. However, due to lower noise margin of dynamic logic performance is not auspicious. This research proposes a N-FinFET based resistive keeper circuit using 45nm PTM FinFET model
Autor:
Mansour H. Assaf, Mahbubul Haque, Riazul Islam, Kazi Fatima Sharif, Satyendra N. Biswas, Voicu Groza
Publikováno v:
2017 International Conference on Innovative Mechanisms for Industry Applications (ICIMIA).
This research proposed a new type of memory cell designed by using only nMOS transistors. The memory cell consumes less power and also occupies minimum amount of silicon area. The stability of the data during successive read operation and noise margi
Autor:
Riazul Islam, Kazi Fatima Sharif, Satyendra N. Biswas, Sunil R. Das, Mansour H. Assaf, Mahbubul Haque, Emil M. Petriu
Publikováno v:
2017 International Conference on Innovative Mechanisms for Industry Applications (ICIMIA).
Designing VLSI circuit using dynamic logic is one of the most area efficient techniques. However, the performance of the dynamic logic is not so promising due to longer time delay and higher leakage power. This research proposes a new model of dynami
Publikováno v:
2016 3rd International Conference on Electrical Engineering and Information Communication Technology (ICEEICT).
In the new era of smart grid in power system, demand side management (DSM) plays a vital role which helps the customers to make the right decision regarding their power consumption thus minimize the peak load demand and provide the best load profile.