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Publikováno v:
Carpathian Journal of Electronic and Computer Engineering. 12:29-36
The fast evolution of battery functioned devices has caused approaches for decreasing power consumption in the memories is substantial. In this paper, a new proposal of SRAM with 8 transistors (8T) has been designed and also the cell itself is tested
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c93d8a2a3553fb51c103962360ef2d02
https://doi.org/10.2478/cjece-2019-0006
https://doi.org/10.2478/cjece-2019-0006
Publikováno v:
In Endocrine Practice May 2023 29(5) Supplement:S47-S47
Publikováno v:
Clinical Case Reports; Feb2022, Vol. 10 Issue 2, p1-6, 6p
Publikováno v:
In Journal of Clinical and Translational Endocrinology: Case Reports December 2022 26
Publikováno v:
International Journal of Reconfigurable and Embedded Systems (IJRES). 9:42
Area efficient and stable memory design is one of the most important tasks in designing system on chip. This research concentrates in designing a new type of hybrid memory model by using only nMOS transistors and memristor.The proposed memory cell is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::529d6880d117b203767b428c40f5df33
https://doi.org/10.11591/ijres.v9.i1.pp42-51
https://doi.org/10.11591/ijres.v9.i1.pp42-51
Publikováno v:
2018 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE).
The high demand for memory devices by decreasing power consumption is significant. SRAM has been under its renewal phase by enduring the ever-increasing delay along with supporting low power applications. A New 10 transistor (lOT) SRAM cell architect
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::da72c0083afd658ee58ac607158756e1
https://doi.org/10.1109/wiecon-ece.2018.8783036
https://doi.org/10.1109/wiecon-ece.2018.8783036
Autor:
Voicu Groza, Satyendra N. Biswas, Abdullah Al Mamun, Riazul Islam, Sunil R. Das, Kazi Fatima Sharif, Mansour H. Assaf, Md. Shah Miran
Publikováno v:
2017 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE).
Dynamic logic is highly in demand for designing low power VLSI circuits. It need less number of transistor though but the performance of the dynamic logic is not so promising due to prolonged contention time and higher leakage power. Present research
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7de4583d5cd2d10e22dd2abd6198080b
https://doi.org/10.1109/iscaie.2017.8074950
https://doi.org/10.1109/iscaie.2017.8074950
Publikováno v:
2017 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE).
This research proposed a new type of memory cell designed by using only nMOS transistors of 16nm, 22nm and 45nm (Arizona State University Predictive Technologies Model) PTM models and memristors. The memory cell consumes less power and also occupies
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::67ede6c10e691ae0c4623ca850e73b75
https://doi.org/10.1109/iscaie.2017.8074946
https://doi.org/10.1109/iscaie.2017.8074946
Publikováno v:
2017 International Conference on Innovative Mechanisms for Industry Applications (ICIMIA).
This research proposed a new design of memory cell of 7T SRAM using 16nm and 45nm (Arizona State University Predictive Technologies Model) PTM models. The memory cell provides larger static noise margin in hold state and a better read operation by co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5e33019dca37b7e3e6bf413800eabf9f
https://doi.org/10.1109/icimia.2017.7975599
https://doi.org/10.1109/icimia.2017.7975599