Ultrathin DPN STI SiON liner for 40nm low-power CMOS technology

Autor: S. C. Chen, Kay Ming Lee, Jone F. Chen, Shoou-Jinn Chang, Chih Ping Lee, Chan Yuan Hu

Publikováno v: Solid-State Electronics. 54:564-567

At sub-40 nm CMOS technology nodes, the implementation of shallow trench isolation (STI) becomes more challenging due to shrinking geometries and stricter device leakage requirements. As device geometries are shrinking, STI liner is also becoming thi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::912ca57879bd876a657ee14ef92f4227
https://doi.org/10.1016/j.sse.2010.01.019

Shallow trench isolation stress modification by optimal shallow trench isolation process for sub-65-nm low power complementary metal oxide semiconductor technology

Autor: Kay Ming Lee, Chan Yuan Hu, Shih Ming Wang, Chih Ping Lee, Shoou-Jinn Chang, S. C. Chen, Jone F. Chen

Publikováno v: Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena. 28:391-397

Shallow trench isolation (STI) induced mechanical stress affects the device behavior in the advanced complementary metal oxide semiconductor (CMOS) technology. This article presents how to use an optimal STI process to reduce transistor mismatch and

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::e57439b643598342dbe3abd3be363a55
https://doi.org/10.1116/1.3359612

Compensation of resist trim process and polygate plasma microloading effect for lithography process window and CD uniformity improvement

Autor: Kuej Chun Hung, Cheng Wen Fan, Kay Ming Lee, Chih Chiang Liu, H T Chuang, Jiunn-Ren Huang

Publikováno v: SPIE Proceedings.

Poly-gate critical dimension (CD) control has become a major concern as technology advances towards the 130nm node. The presence of optical proximity and plasma microloading effects in today's IC fabrication has a severe impact on through-pitch CD un

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::e76477d444af3032cb6b337ff75820a3
https://doi.org/10.1117/12.473429

Shallow trench isolation stress modification by optimal shallow trench isolation process for sub-65-nm low power complementary metal oxide semiconductor technology.

Autor: Chan-Yuan Hu, Chen, Jone F., Shih-Chih Chen, Shoou-Jinn Chang, Shih-Ming Wang, Chih-Ping Lee, Kay-Ming Lee

Publikováno v: Journal of Vacuum Science & Technology: Part B-Nanotechnology & Microelectronics; Mar2010, Vol. 28 Issue 2, p391-397, 7p, 3 Diagrams, 1 Chart, 10 Graphs