Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Kaushik Narayanun"'
Autor:
Bonita Bhaskaran, Sanmitra Banerjee, Kaushik Narayanun, Shao-Chun Hung, Seyed Nima Mozaffari Mojaveri, Mengyun Liu, Gang Chen, Tung-Che Liang
Publikováno v:
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3be275da2e1de370a86aba1441bc82db
https://doi.org/10.1145/3508352.3561122
https://doi.org/10.1145/3508352.3561122
Autor:
Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Kaushik Narayanun, Shantanu Sarangi, Francisco Da Silva, Joe Sarmiento, Smbat Tonoyan, Ashwin Chintaluri, Animesh Khare, Milind Sonawane, Ashish Kumar, Anitha Kalva, Alex Hsu, Jayesh Pandey
Publikováno v:
2022 IEEE 40th VLSI Test Symposium (VTS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8363c45c201b9caa44d71a5134b4a81d
https://doi.org/10.1109/vts52500.2021.9794146
https://doi.org/10.1109/vts52500.2021.9794146
Autor:
Jonathon E. Colburn, Seyed Nima Mozaffari, Kaushik Narayanun, Shantanu Sarangi, Vinod Pagalone, Ayub Abdollahian, Bonita Bhaskaran
Publikováno v:
ITC
The Power Distribution Network (PDN) is designed for worst-case power-hungry functional use-cases. Most often Design for Test (DFT) scenarios are not accounted for, while optimizing the PDN design. Automatic Test Pattern Generation (ATPG) tools typic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::62242e94db505e1ce83da9759385bb1f
https://doi.org/10.1109/itc44170.2019.9000171
https://doi.org/10.1109/itc44170.2019.9000171
Publikováno v:
VTS
Scan compression is widely used in high-volume testing of complex integrated circuits. With an increase in design complexity, the increased density of unknown (X) values from output responses reduces compression efficiency. In order to effectively bl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a3b42654982666d07264f7e1d48778fe
https://doi.org/10.1109/vts.2017.7928956
https://doi.org/10.1109/vts.2017.7928956
Publikováno v:
VTS
Test Mode power can be 5X higher than functional power in GPUs, while the power grid is designed only for worst-case functional toggle. The large simultaneous switching noise induced on the power rails during at-speed capture testing is constrained b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6f5c9552547439e9aa0939d990c44994
https://doi.org/10.1109/vts.2016.7477310
https://doi.org/10.1109/vts.2016.7477310
Autor:
Bonita Bhaskaran, Ran Wang, Amit Sanghani, Karthikeyan Natarajan, Kaushik Narayanun, Ayub Abdollahian, Krishnendu Chakrabarty
Publikováno v:
VTS
We present a programmable method for shift-clock stagger assignment to reduce power supply noise during system-on-chip (SoC) testing. An SoC design is typically composed of several blocks and two neighboring blocks that share the same power rails sho
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a5248b358c2c9777a02c28b694364050
https://doi.org/10.1109/vts.2016.7477289
https://doi.org/10.1109/vts.2016.7477289
Publikováno v:
ACS/IEEE International Conference on Computer Systems and Applications, 2003. Book of Abstracts..
Summary form only given, as follows. The UCSC Kestrel parallel processor is a high performance SIMD computer implemented using a linear systolic array. In our current system systolic shared registers (SSR's) are used to combine computation and commun
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cc516d72619e4a1018eb81ced05b56e5
https://doi.org/10.1109/aiccsa.2003.1227443
https://doi.org/10.1109/aiccsa.2003.1227443
Publikováno v:
ACS/IEEE International Conference on Computer Systems & Applications, 2003. Book of Abstracts; 2003, p6-6, 1p