Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Katsuhiro Seta"'
Autor:
F. Sano, Hiroshi Momose, Takayasu Sakurai, K. Matsuda, Yohji Watanabe, Tetsu Nagamatsu, Y. Niitsu, Katsuhiro Seta, A. Chiba, Hiroyuki Miyakawa, Hiroyuki Hara
Publikováno v:
IEEE Journal of Solid-State Circuits. 27:1579-1584
BiCMOS standard cell macros, including a 0.5-W 3-ns register file, a 0.6-W 5-ns 32-kbyte cache, a 0.2-W 3-ns table look-aside buffer (TLB), and a 0.1-W 3-ns adder, are designed with a 0.5- mu m BiCMOS technology. A supply voltage of 3.3 V is used to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7e93a13c4f8cf7924feeaa47898753c0
https://doi.org/10.1109/4.165339
https://doi.org/10.1109/4.165339
Autor:
K. Maeguchi, Hiroyuki Hara, F. Sano, S. Kobayashi, Katsuhiro Seta, Hiroshi Momose, Yohji Watanabe, M. Noda, Tetsu Nagamatsu, Y. Niitsu, Takayasu Sakurai, Hiroyuki Miyakawa
Publikováno v:
IEEE Journal of Solid-State Circuits. 26:1615-1620
A channelless gate array has been realized using 0.5- mu m BiCMOS technology integrating more than two million transistors on a 14-mm*14.4-mm chip. A small-size PMOS transistor and a small-size inverter are added to the conventional BiNMOS gate to fo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e790724c8662536cedaa9c110b567dcf
https://doi.org/10.1109/4.98980
https://doi.org/10.1109/4.98980
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction
Publikováno v:
DATE
This paper presents a design flow for an improved selective multi-threshold(Selective-MT) circuit. The Selective-MT circuit is improved so that plural MT-cells can share one switch transistor. We propose the design methodology from RTL(Register Trans
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b54d8f59498731be824ed48cfd223d99
https://doi.org/10.1109/date.2005.68
https://doi.org/10.1109/date.2005.68
Autor:
F. Sano, Katsuhiro Seta, Hiroyuki Miyakawa, Y. Niitsu, Yohji Watanabe, K. Matsuda, Hiroshi Momose, Tetsu Nagamatsu, A. Chiba, Takayasu Sakurai, H. Kara, Tadahiro Kuroda, S. Kobayashi
Publikováno v:
1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
BiCMOs standard-cell macros, including a 0.5-W, 3.0-ns register file, a 0.6-W, 5.0-ns 32-kB cache, a 0.2-W, 2.5-ns table look-aside buffer (TLB), and a 0.1-W, 3.0-ns adder, are presented based on a 0.5- mu m BiCMOs technology. These power consumption
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::df18b1ded9ffa05caf80ba1ae51f66c6
https://doi.org/10.1109/isscc.1992.200403
https://doi.org/10.1109/isscc.1992.200403
Autor:
Tadahiro Oku, Takayasu Sakurai, Tatsuhiko Demura, Kazukuni Kitagaki, S. Ishiwata, Hiroyuki Hara, S. Michinaka, Takayoshi Shimazawa, Tomoo Yamakage, G. Otomo, Tetsu Nagamatsu, S. Suzuki, N. Goto, T. Oto, Katsuhiro Seta, Toshinori Odaka, K. Maeguchi, Yoshiharu Uetani, Masataka Matsui
Publikováno v:
Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.
This MPEG2 video decoder LSI decodes MPEG2 standard bit streams. The compression algorithm in the MPEG2 is based on discrete cosine transform (DCT), variable length coding, and motion compensation similar to the MPEG1, the earlier standard. However,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7176aebc1b6a53ed2eac1afba3ee930e
https://doi.org/10.1109/isscc.1994.344721
https://doi.org/10.1109/isscc.1994.344721
Autor:
G. Otomo, Katsuhiro Seta, Shinji Mita, Tetsu Nagamatsu, Y. Uetani, Hiroyuki Hara, Takayasu Sakurai, T. Oto, Yohji Watanabe, F. Sano, Takayoshi Shimazawa, A. Chiba, Masataka Matsui, Lee-Sup Kim, K. Matsuda
Publikováno v:
Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.
Improving the performance of fully dedicated macrocells is key to realizing HDTV-resolution video de/compression LSIs operating at more than 100 MHz, having reasonable power consumption and chip size small enough for consumer applications. Existing c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ee56fe1fc97dd8cdf037ff678d755f92
https://doi.org/10.1109/isscc.1994.344720
https://doi.org/10.1109/isscc.1994.344720
Publikováno v:
Proceedings ISSCC '95 - International Solid-State Circuits Conference.
High-speed and low-power are required for multimedia LSIs, since portability with battery operation is sometimes the key factor for multimedia equipment, while delivering giga operations per second (GOPS) processing power for digital video use. To un
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d98343b8d13641eb5d6c836fa8519dab
https://doi.org/10.1109/isscc.1995.535572
https://doi.org/10.1109/isscc.1995.535572
Publikováno v:
ISLPED
This paper describes an automated design technique to selectively use multi-threshold CMOS (MTCMOS) in a cell-by-cell fashion. MT cells consisting of low-Vth transistors and high-Vth sleep transistors are assigned to critical paths, while high-Vth ce
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::098d4be0313a49c2250943853bc56bd3
https://doi.org/10.1109/lpe.2002.146737
https://doi.org/10.1109/lpe.2002.146737
Autor:
Masahiko Motoyama, M. Ishibe, K. Yamaura, Sumio Tanaka, Hiroshi Momose, E. Kamagata, Shoichi Shimizu, Yasuro Shobatake, Y. Niitsu, Kenji Sakaue, S. Takatsuka, M. Noda, Katsuhiro Seta, Y. Shimojoh
Publikováno v:
1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8dea2f67f6e41a476e7dd2cbf90815b0
https://doi.org/10.1109/isscc.1991.689144
https://doi.org/10.1109/isscc.1991.689144
Autor:
Hiroyuki Hara, Takayasu Sakurai, Makoto Noda, Tetsu Nagamatsu, Katsuhiro Seta, Hiroshi Momose, Youichirou Niitsu, Hiroyuki Miyakawa, Yoshinori Watanabe
Publikováno v:
High-Performance System Design; 1999, p112-116, 5p