Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Katsuhiko Hoya"'
Autor:
Soo Man Seo, Hisanori Aikawa, Soo Gil Kim, Toshihiko Nagase, Yuich Ito, Tae Jung Ha, Kenichi Yoshino, Bo Kyung Jung, Tadaaki Oikawa, Ku Youl Jung, Hyun In Moon, Bum Su Kim, Fumiyoshi Matsuoka, Kosuke Hatsuda, Katsuhiko Hoya, Seiyon Kim, Sung-Hoon Lee, Myung-Hee Na, Seon Yong Cha
Publikováno v:
2022 International Electron Devices Meeting (IEDM).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::93062041cdb27bb915b9189a66ed2cfe
https://doi.org/10.1109/iedm45625.2022.10019549
https://doi.org/10.1109/iedm45625.2022.10019549
Autor:
Katsuhiko Hoya, Kosuke Hatsuda, Yusuke Shirota, Yohii Watanabe, Tatsunori Kanai, Kenji Tsuchida
Publikováno v:
VLSI-DAT
Memory hierarchy (Fig. 1) is one of the most essential component of any computing system. Non-volatile random access memory (NVRAM) technologies, such as PCRAM, STT-MRAM and ReRAM, have been massively produced in recent years and expected to bridge t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::11bad160ceb358df5fd56ade4c469e27
https://doi.org/10.1109/vlsi-dat.2019.8741675
https://doi.org/10.1109/vlsi-dat.2019.8741675
Autor:
Shuso Fujii, Daisaburo Takashima, Ryu Ogiwara, Daisuke Hashimoto, Akihiro Nitayama, Shinichiro Shiratake, Ryo Fukuda, Susumu Shuto, Yohji Watanabe, Hidehiro Shiga, Tohru Ozaki, Katsuhiko Hoya, Iwao Kunishima, Tadashi Miyakawa, Sumiko Doumae, Takeshi Hamamoto, Hiroyuki Kanaya, Ryosuke Takizawa, Koji Yamakawa
Publikováno v:
ISSCC
A ferroelectric capacitor overdrive technique with shield-bitline drive has been demonstrated and verified by a 130 nm 576 Kb test chip with a 0.7191 μm2 cell. First, cell signal degradation and bitline-to-bitline coupling noise worsened by wide cel
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5daa454ca9ff7463fb3e94791bd14491
https://doi.org/10.1109/jssc.2011.2159053
https://doi.org/10.1109/jssc.2011.2159053
Autor:
Shinichiro Shiratake, Yoshinori Kumura, S. Ohtsuki, Hitoshi Shiga, Sumiko Doumae, Iwao Kunishima, T. Ozaki, Daisaburo Takashima, Tadashi Miyakawa, Ryu Ogiwara, Akihiro Nitayama, Koji Yamakawa, Katsuhiko Hoya, Syuso Fujii, Susumu Shuto
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18:1745-1752
A 64-Mb chain ferroelectric RAM (chainFeRAM) is fabricated using 130-nm 3-metal CMOS technology. A newly developed quad bitline architecture, which combines folded bitline configuration with shield bitline scheme, eliminates bitline-bitline (BL-BL) c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a05654e47ec1032b385902092e35fa7e
https://doi.org/10.1109/tvlsi.2009.2034380
https://doi.org/10.1109/tvlsi.2009.2034380
Autor:
Daisuke Hashimoto, Akihiro Nitayama, Daisaburo Takashima, Takeshi Hioka, Yoshiro Shimojo, Hidehiro Shiga, Yuki Yamada, Koji Yamakawa, Katsuhiko Hoya, Toyoki Taguchi, Shoichi Shimizu, Ryu Ogiwara, Hisaaki Nishimura, Tohru Ozaki, Yohji Watanabe, Shinichiro Shiratake, Sumiko Doumae, Iwao Kunishima, Tohru Furuyama, Tadashi Miyakawa, Hiroyuki Kanaya, Souichi Yamazaki, Shuso Fujii, Fumiyoshi Matsuoka, Yasushi Nagadomi, Ryo Fukuda, Ryosuke Takizawa, Yoshinori Kumura, Mitsumo Kawano, Susumu Shuto, Takeshi Hamamoto, Yoshihiro Minami, Kosuke Hatsuda
Publikováno v:
ISSCC
An 87.7 mm2 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1fda70ed57de6c8e43a679a78faba8b0
https://doi.org/10.1109/jssc.2009.2034414
https://doi.org/10.1109/jssc.2009.2034414
Autor:
Iwao Kunishima, Masahiro Kamoshida, Y. Itoh, Ryu Ogiwara, Koji Yamakawa, Yukihito Oowaki, Sumiko Doumae, Yoshiaki Takeuchi, Hiroyuki Kanaya, M. Aoki, Daisaburo Takashima, Katsuhiko Hoya, T. Ozaki, Tadashi Miyakawa
Publikováno v:
IEEE Journal of Solid-State Circuits. 36:1713-1720
This paper demonstrates the first 8-Mb chain ferroelectric RAM (chain FeRAM) with 0,25-/spl mu/m 2-metal CMOS technology. A small die of 76 mm/sup 2/ and a high average cell/chip area efficiency of 57.4 % have been realized by introducing not only ch
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1328823be39788f7539d6e6dfd274a0e
https://doi.org/10.1109/4.962293
https://doi.org/10.1109/4.962293
Autor:
Ryu Ogiwara, Syuso Fujii, Iwao Kunishima, Daisaburo Takashima, Yoshinori Kumura, Hitoshi Shiga, S. Ohtsuki, Akihiro Nitayama, Shinichiro Shiratake, Sumiko Doumae, Tadashi Miyakawa, T. Ozaki, Koji Yamakawa, Katsuhiko Hoya, Susumu Shuto
Publikováno v:
ISSCC
A 64Mb chain FeRAM implemented in 0.13mum 3M CMOS technology is described. A quad-BL architecture reduces the die area by 6.5% and realizes 87.5mm2 die with an effective cell-size of 0.7191mum2 while eliminating BL-BL coupling noise. A high-speed ECC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::584065a7f06dedbb7ebf7903987f8b3b
https://doi.org/10.1109/isscc.2006.1696078
https://doi.org/10.1109/isscc.2006.1696078
Publikováno v:
2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).
This paper proposes the new bitline/plateline operation scheme for 32 Mb chainFeRAM, which overcomes these two problems and also overcomes the problem of large array current due to the grounded bitline precharge scheme used for FeRAM.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d1803c226e8ddfbd0fd117b40ab45b86
https://doi.org/10.1109/vlsic.2003.1221191
https://doi.org/10.1109/vlsic.2003.1221191
Autor:
Shinichiro Shiratake, Iwao Kunishima, Daisaburo Takashima, Gerhard Beitel, Koji Yamakawa, Michael Jacob, Thomas Roehr, Katsuhiko Hoya, Yoshiaki Takeuchi, Jörg Wohlfahrt, T. Ozaki, Nicolas Nagel, Ryu Ogiwara, Tadashi Miyakawa, Norbert Rehm, Kohei Oikawa, H.-O. Joachim, Masahiro Kamoshida, Sueo Sugimoto
Publikováno v:
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
This paper demonstrates the 32-Mb chain ferroelectric RAM (chain FeRAM) with 0.2-/spl mu/m three-metal CMOS technology. A small die size of 96 mm/sup 2/ and a high cell/chip area efficiency of 65.6% are realized not only by the small cell size using
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c8a6dd1fb60a37827e9564fc390ffa82
https://doi.org/10.1109/isscc.2003.1234302
https://doi.org/10.1109/isscc.2003.1234302