Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Katsuhiko Degawa"'
Publikováno v:
2016 IEEE 21st International Mixed-Signal Testing Workshop (IMSTW).
Propagation delay variation of the threshold detection comparator in current-day level-crossing ADCs is a fundamental impediment to their performance. This paper reviews why commonly used threshold detection comparators can be inappropriate to detect
Autor:
Mani Soma, Kouichiro Uekusa, Katsuhiko Degawa, Takahiro Yamaguchi, Masahiro Ishida, Masayuki Kawabata
Publikováno v:
ITC
This paper proposes a new method for directly measuring alias-free aperture jitter in an ADC output. Both the average ENOB and the worst-case ENOB due to aperture jitter are also measured after the elimination of the aliasing noise. Because it adds o
Autor:
Hiroshi Nakashima, Hiroshi Inokawa, Koji Sumitomo, Takafumi Aoki, Touichiro Goto, Kazuaki Furukawa, Katsuhiko Degawa, Keiichi Torimitsu
Publikováno v:
Japanese Journal of Applied Physics. 45:4285-4289
We report the electrical characteristics of gold nanogap devices modified by conjugated molecules with thiol endgroups. Gold nanogap electrodes with a nominal gap distance of between 1–2 nm were fabricated by double oblique deposition from opposite
Autor:
Mani Soma, Katsuhiko Degawa, Kunihiro Asada, Takafumi Aoki, Mohamed Abbas, Satoshi Komatsu, Takahiro Yamaguchi, Yasuo Furukawa
Publikováno v:
ITC
This paper introduces a new Level-Crossing ADC (LCADC) architecture which employs the novel use of a clocked comparator. The proposed LCADC can measure a timing noise spectrum with wide dynamic range and wide frequency range. An extension of the unde
Autor:
Mani Soma, Mohamed Abbas, Takafumi Aoki, Kunihiro Asada, Yasuo Furukawa, Takahiro Yamaguchi, Satoshi Komatsu, Katsuhiko Degawa
Publikováno v:
ISCAS
This paper presents an improved design for a Level-Crossing ADC (LCADC) that incorporates both an equivalent-time method and a clocked comparator. The LCADC is experimentally validated using a 65 nm clocked comparator.
Publikováno v:
ISMVL
This paper proposes a high-level design method of multiple-valued arithmetic circuits. The proposed method uses a cell-based approach with a dedicated hardware description language called ARITH. By using ARITH, we can describe and verify any binary/m
Publikováno v:
ISMVL
This paper presents a novel approach to designing multiple-valued arithmetic circuits based on a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). By using CTDs, we can derive possible variations of addition algorithm
Autor:
Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Katsuhiko Nishiguchi
Publikováno v:
ISMVL
This paper presents a circuit design of a Ternary Content-Addressable Memory (TCAM) using Single- Electron Transistors (SETs). The proposed TCAM cell employs a SET-based ternary memory and a dual-gate SET for ternary data matching. The multi-level fu
Publikováno v:
ISMVL
Scopus-Elsevier
Scopus-Elsevier
This paper presents a circuit design of a two-bit-per-cell content-addressable memory (CAM) using single-electron transistors (SETs). The key ideas of the proposed CAM architecture are (i) four-level data storage function implementing by a SET-based
Publikováno v:
ISMVL
This paper presents a Field-Programmable Digital Filter (FPDF) IC that employs carry-propagation-free redundant arithmetic algorithms for faster computation and multiple-valued current-mode circuit technology for high-density low-power implementation