Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Kathirgamar Aingaran"'
Autor:
Paul N. Loewenstein, Stephen E. Phillips, Sivaramakrishnan Ram, Curtis McAllister, Serena Leung, David Smentek, Sumti Jairath, Kathirgamar Aingaran, Thomas M. Wicki, Zoran Radovic, Georgios Konstadinidis
Publikováno v:
IEEE Micro. 35:36-45
The Oracle Sparc M7 processor more than triples the throughput of the Sparc M6 processor, while increasing per-thread performance, power efficiency, and I/O bandwidth. M7 contains 32 8-thread, dual-issue, out-of-order Sparc cores. To minimize L3 cach
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c1a908654ce4a7e26ddb266d7ba9c548
https://doi.org/10.1109/mm.2015.35
https://doi.org/10.1109/mm.2015.35
Publikováno v:
Hot Chips Symposium
1 SW in Silicon is custom hardware targeted at specific higher level functions traditionally implemented in software 2 Cloud based applications, especially analytics, offer many opportunities for SW in Silicon features 3 SW in Silicon in SPARC M7 pro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b385d921ed82a3e4a83847f1e0a20ef7
https://doi.org/10.1109/hotchips.2016.7936220
https://doi.org/10.1109/hotchips.2016.7936220
Publikováno v:
IEEE Micro. 25:21-29
The Niagara processor implements a thread-rich architecture designed to provide a high-performance solution for commercial server applications. This is an entirely new implementation of the Sparc V9 architectural specification, which exploits large a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::117018da3b099ca86d49a884506c2681
https://doi.org/10.1109/mm.2005.35
https://doi.org/10.1109/mm.2005.35
Autor:
J. Kaku, J. Hart, S. Vishwanthaiah, D. Murata, G. Yee, Yet-Ping Pai, Raymond A. Heald, S. Nguyen, Kathirgamar Aingaran, Song Kim, Chin Kim, E. You, D. Greenley, G. Lauterbach, J. Grinberg, H. McIntyre, Roger Y. Lo, G. Gouldsberry, K. Shin, Wen-Jay Hsu, Chaim Amir, T. Horel, A. Mehta, J. Wu, F. Klass, P. Dixit, M. Ang, S. Patel, H. Kwan, M. Boland, Kenway Tam
Publikováno v:
IEEE Journal of Solid-State Circuits. 35:1526-1538
This quad-issue processor achieves 1-GHz operation through improved dynamic circuit techniques in critical paths and a more extensive on-chip memory system which scales in both bandwidth and latency. Critical logic paths use domino, delayed clocked d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::193ee259cf3f3bc2c4e86ab5eeb7d519
https://doi.org/10.1109/4.881196
https://doi.org/10.1109/4.881196
Autor:
Raymond A. Heald, Chaim Amir, G. Yee, Kathirgamar Aingaran, R. Wang, C. Truong, A. Das, A. Mehta, F. Klass
Publikováno v:
IEEE Journal of Solid-State Circuits. 34:712-716
In an attempt to reduce the pipeline overhead, a new family of edge-triggered flip-flops has been developed. The flip-flops belong to a class of semidynamic and dynamic circuits that can interface to both static and dynamic circuits. The main feature
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::43cac84c876e57624ca837769cb29bba
https://doi.org/10.1109/4.760383
https://doi.org/10.1109/4.760383
Autor:
E. You, J. Mohd, F. Klass, Sai-Keung Dong, Chin-Man Kim, Chaim Amir, J. Mitral, Kathirgamar Aingaran
Publikováno v:
ISQED
Although digital circuits are inherently immune to most sources of noise, the scaling of supply voltages and MOSFET threshold voltages has resulted in lowered noise margins. Most CMOS circuits continue to have considerable immunity to power supply an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::78b30dbc3baa3f6ff81dc4ad43a5c810
https://doi.org/10.1109/isqed.2000.838930
https://doi.org/10.1109/isqed.2000.838930