Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Katayoon Basharkhah"'
Autor:
Zahra Mahdavi, Nooshin Nosrati, Zainalabedin Navabi, Katayoon Basharkhah, Hanieh Totonchi Asl
Publikováno v:
DTIS
This paper is on a RISCV-like processor and developing a virtual tester for it. We define a Virtual Tester as a testbench in an HDL that performs test functions as an automatic test equipment does. The virtual tester is used for developing test sets,
Publikováno v:
ETS
Convolution accelerators used in safety-critical systems require robustness and resilience to runtime faults. In this paper, we design a processing element for the convolution accelerators that support a row-stationary dataflow. The proposed processi
Autor:
Katayoon Basharkhah, Nooshin Nosrati, Saba Yousefzadeh, Seyedeh Maryam Ghasemi, Zainalabedin Navabi, Maryam Rajabalipanah
Publikováno v:
DDECS
The work presented in this paper is on reconfigurable accelerators for the implementation of iterative computations and loops that form the core computations of applications like those in digital signal processing and machine learning. The accelerato
Publikováno v:
VTS
At the system-level, cores are put together using interconnects that we refer to as high-level communication links. This paper presents an abstract interconnect model for cores connecting to each other to estimate, and thus model, crosstalk noise res
Publikováno v:
Wireless Personal Communications. 98:1913-1929
Adaptive beamformers are designed with the aim of detection of noise and intentional destructive interference and then removing them from the desired signal. This is done by placing high attenuation in the direction of the destructive signal in the r
Autor:
Zainalabedin Navabi, Seyedeh Maryam Ghasemi, Katayoon Basharkhah, Nooshin Nosrati, Saba Yousefzadeh, Maryam Rajabalipanah
Publikováno v:
DFT
Because of heavy repeated computations and concurrency in the execution of many machine learning applications, embedded hardware architectures based on reconfigurable accelerators have emerged as a convenient and efficient means of hardware implement
Publikováno v:
European Journal of Electrical Engineering and Computer Science. 3
A wide variety of digital communication systems are encountered with high computational tasks. QR decomposition is one of such algorithms that can be implemented on FPGAs as a solution to large complex matrix inversion problems. A flexible vector pro
Autor:
Katayoon Basharkhah, Christoph Grimm, Nooshin Nosrati, Zainalabedin Navabi, Rezgar Sadeghi, Carna Zivkovic
Publikováno v:
EWDTS
Nowadays electronic systems are moving toward more complex designs with various computation and communication blocks. In addition to test requirements for individual system blocks, the functionality of the overall system must also be tested. Conventi
Autor:
Jaan Raik, Zainalabedin Navabi, Rezgar Sadeghi, Katayoon Basharkhah, Nooshin Nosrati, Saba Yousefzadeh, Maksim Jenihhin
Publikováno v:
EWDTS
Hardware implementation of many of today's applications such as those in automotive, telecommunication, bio, and security, require heavy repeated computations, and concurrency in the execution of these computations. These requirements are not easily
Publikováno v:
EWDTS
ion alongside with multi-level modeling of embedded real-time systems, such as ADAS applications, has gained attention for system analysis and hardware realization. Due to the complexity of the state of art embedded digital signal processing, pre-eva