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Publikováno v:
2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).
The capacitor-less LDO regulator with slew-rate enhancement disabling scheme has been introduced and postlayout simulated in 2P4M 0.35-μm CMOS process. The output voltage can be adjusted on-the-fly from 0.9 to 1.6 V with minimum supply voltage of 1.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::34438120ca27b6180a02154742321632
https://doi.org/10.1109/edssc.2015.7285081
https://doi.org/10.1109/edssc.2015.7285081
