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ADIC: Anomaly Detection Integrated Circuit in 65nm CMOS utilizing Approximate Computing

Autor: Kar, Bapi, Gopalakrishnan, Pradeep Kumar, Bose, Sumon Kumar, Roy, Mohendra, Basu, Arindam

In this paper, we present a low-power anomaly detection integrated circuit (ADIC) based on a one-class classifier (OCC) neural network. The ADIC achieves low-power operation through a combination of (a) careful choice of algorithm for online learning

Externí odkaz: http://arxiv.org/abs/2008.09442

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ADEPOS: A Novel Approximate Computing Framework for Anomaly Detection Systems and its Implementation in 65nm CMOS

Autor: Bose, Sumon Kumar, Kar, Bapi, Roy, Mohendra, Gopalakrishnan, Pradeep Kumar, Lei, Zhang, Patil, Aakash, Basu, Arindam

Publikováno v: Preprint TCAS-I 2019

To overcome the energy and bandwidth limitations of traditional IoT systems, edge computing or information extraction at the sensor node has become popular. However, now it is important to create very low energy information extraction or pattern reco

Externí odkaz: http://arxiv.org/abs/1912.01853

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Exploring the Scope of Unconstrained Via Minimization by Recursive Floorplan Bipartitioning

Autor: Kar, Bapi, Sur-Kolay, Susmita, Mandal, Chittaranjan

Random via failure is a major concern for post-fabrication reliability and poor manufacturing yield. A demanding solution to this problem is redundant via insertion during post-routing optimization. It becomes very critical when a multi-layer routing

Externí odkaz: http://arxiv.org/abs/1811.05161

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ADEPOS: Anomaly Detection based Power Saving for Predictive Maintenance using Edge Computing

Autor: Bose, Sumon Kumar, Kar, Bapi, Roy, Mohendra, Gopalakrishnan, Pradeep Kumar, Basu, Arindam

In industry 4.0, predictive maintenance(PM) is one of the most important applications pertaining to the Internet of Things(IoT). Machine learning is used to predict the possible failure of a machine before the actual event occurs. However, the main c

Externí odkaz: http://arxiv.org/abs/1811.00873

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Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model

Autor: Kar, Bapi, Sur-Kolay, Susmita, Mandal, Chittaranjan

Multiple design iterations are inevitable in nanometer Integrated Circuit (IC) design flow until desired printability and performance metrics are achieved. This starts with placement optimization aimed at improving routability, wirelength, congestion

Externí odkaz: http://arxiv.org/abs/1810.12789

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STAIRoute: Early Global Routing using Monotone Staircases for Congestion Reduction

Autor: Kar, Bapi, Sur-Kolay, Susmita, Mandal, Chittaranjan

With aggressively shrinking process nodes, physical design methods face severe challenges due to poor convergence and uncertainty in getting an optimal solution. An early detection of potential failures is thus mandated. This has encouraged to devise

Externí odkaz: http://arxiv.org/abs/1810.10412

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A Stacked Autoencoder Neural Network based Automated Feature Extraction Method for Anomaly detection in On-line Condition Monitoring

Autor: Roy, Mohendra, Bose, Sumon Kumar, Kar, Bapi, Gopalakrishnan, Pradeep Kumar, Basu, Arindam

Condition monitoring is one of the routine tasks in all major process industries. The mechanical parts such as a motor, gear, bearings are the major components of a process industry and any fault in them may cause a total shutdown of the whole proces

Externí odkaz: http://arxiv.org/abs/1810.08609

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