Zobrazeno 1 - 10
of 31
pro vyhledávání: '"Kaori Tai"'
Publikováno v:
Neurosonology. 28:49-53
Autor:
S. Yamaguchi, Kaori Tai, S. Kadomura, Takashi Ando, Heiji Watanabe, H. Iwamoto, Shinichi Yoshida, T. Hirano
Publikováno v:
IEEE Transactions on Electron Devices. 56:3223-3227
A record high electron mobility (248 cm2/V middots at E eff of 1 MV/cm) was obtained at T inv of 1.47 nm, with a band-edge effective work function, by a Hf-Si/HfO2 stack using gate-last process, resulting in I ON of 1178 muA/mum (I OFF of 100 nA/ mum
Autor:
Y. Tateshita, T. Hirano, Naoki Nagashima, Hitoshi Wakabayashi, Kaori Tai, Satoru Mayuzumi, Masanori Tsukamoto, Masashi Nakata, S. Yamaguchi, Shinya Yamakawa
Publikováno v:
IEEE Transactions on Electron Devices. 56:620-626
Newly proposed mobility-booster technologies are demonstrated for metal/high-k gate-stack n- and pMOSFETs. The process combination of top-cut SiN dual stress liners and damascene gates remarkably enhances local channel stress particularly for shorter
Autor:
Hayato Iwamoto, Yukio Tagawa, Kazuaki Tanaka, Masaharu Oshima, Masanori Tsukamoto, Ryo Yamamoto, J. Wang, Yoshiya Hagimoto, Shingo Kadomura, Takayuki Uemura, Naoki Nagashima, Saori Kanda, Y. Tateshita, Koji Watanabe, Hitoshi Wakabayashi, Masaki Saito, Kaori Tai, Tomoyuki Hirano, Itaru Oshiyama, S. Yamaguchi, Takashi Ando, Satoshi Toyoda
Publikováno v:
Japanese Journal of Applied Physics. 47:2379-2382
In this paper, we demonstrate a wet treatment for the HfSix/HfO2 gate stack of n-type metal oxide semiconductor field effect transistor (nMOSFET) fabricated by a gate-last process in order to scale down the electrical thickness at inversion state Tin
Autor:
Yukio Tagawa, Hitoshi Wakabayashi, Y. Tateshita, Tomoyuki Hirano, Kazuki Tanaka, Naoki Nagashima, S. Yamaguchi, Kaori Tai, Sayuri Kanda, Hayato Iwamoto, Masaki Saito, Mayumi Yamanaka, Takashi Ando, Masanori Tukamoto, Shingo Kadomura, Masashi Nakata, Itaru Oshiyama, Salam Kazi, Ryo Yamamoto
Publikováno v:
Japanese Journal of Applied Physics. 47:2345-2348
We propose a fluorine (F) treatment technique that is suitable for threshold voltage (Vth) modulation in p-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs) with the atomic layer deposition (ALD) TiN/HfO2 gate structure. A wor
Autor:
Hitoshi Abe, Shigeru Fujita, Kojiro Nagaoka, Kaori Tai, Toshiaki Hasegawa, Takashi Suzuki, Tomoyuki Hirano, Ryota Katsumata, Jun Idebuchi, Hayato Iwamoto, Naoyuki Sato, Takashi Ando, Shingo Kadomura, Hajime Ugajin, Koji Watanabe, Susumu Hiyama, Atsushi Okuyama
Publikováno v:
Japanese Journal of Applied Physics. 45:3165-3169
In this study, the potential of HfSiON as the node dielectric of deep-trench (DT) capacitors was investigated for the first time. It was found out that a uniform thickness and a uniform depth profile of each component in DT can be obtained by the ALD
Publikováno v:
Journal of Applied Physics. 85:3132-3138
The effect of the preamorphization implantation (PAI) process on TiSi2 phase transformation has been investigated by using arrays of submicron TiSi2 lines. The C49–C54 transformation of TiSi2 during annealing is promoted by the PAI process. The pro
Publikováno v:
Physical Review B. 49:7394-7399
We have investigated Ge/SiGe strained-barrier quantum-well structures using photoreflectance spectroscopy. On the basis of the \ensuremath{\Gamma}-point transition energies associated with the Ge quantum well, the band offset at the heterojunction be
Publikováno v:
Journal of Applied Physics. 85:2988-2990
Microstructural characteristics of C49–TiSi2 in narrow lines have been investigated by transmission electron microscopy. The C49–TiSi2 formed by a preamorphization treatment exhibits small grain size and heavily faulted structures. C54 grains are
Autor:
T. Hirano, Yuki Miyanami, Y. Tateshita, Shinya Yamakawa, K. Kugimiya, Kaori Tai, Naoki Nagashima, Yoshiaki Kikuchi, Tadayuki Kimura, R. Yamamoto, K. Nagano, J. Wang, Shingo Kadomura, S. Yamaguchi, S. Kanda, T. Ohno, Masanori Tsukamoto, Masaki Saito, Hayato Iwamoto, Hitoshi Wakabayashi, Y. Tagawa
Publikováno v:
2007 IEEE Symposium on VLSI Technology.
Novel channel-stress enhancement technology on damascene gate process with eSiGe S/D for pFET is demonstrated. It is found for the first time that the damascene gate process featured by the dummy gate removal is more effective in increasing channel s