Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Kang-Wei Hsueh"'
Publikováno v:
2009 IEEE Asian Solid-State Circuits Conference.
A 5-th order bandpass filter is implemented in this paper. The filter can perform SAW filter function required in the tuner. In this design, leap-frog synthesis is used and the Active-RC topology is implemented. To save power consumption, the amplifi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8974bc48ac4580cdb8f7199babaa6840
https://doi.org/10.1109/asscc.2009.5357172
https://doi.org/10.1109/asscc.2009.5357172
Publikováno v:
2008 IEEE Asian Solid-State Circuits Conference.
A 3-order multi-bit continuous-time delta-sigma ADC with clock timing calibration circuit is presented. The clock timing calibration circuit is proposed to ensure the stability of the continuous-time delta-sigma ADC and relax the bandwidth requiremen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::211ab753ecc6af7e27fcae2f668ce461
https://doi.org/10.1109/asscc.2008.4708804
https://doi.org/10.1109/asscc.2008.4708804
Publikováno v:
ISSCC
This paper demonstrates a IV 200MS/s pipelined ADC with digital background calibration in 65nm digital CMOS process.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::956e20b9e6bb2495698bdb50bb7fb996
https://doi.org/10.1109/isscc.2008.4523299
https://doi.org/10.1109/isscc.2008.4523299
Publikováno v:
2009 IEEE Asian Solid-State Circuits Conference; 2009, p53-56, 4p
Publikováno v:
2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers; 2008, p546-634, 89p