Zobrazeno 1 - 10
of 22
pro vyhledávání: '"Kang-Il Cho"'
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 70:401-405
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 68:1645-1649
This brief presents a second-order discrete-time (DT) modified feed-forward (FF) delta-sigma modulator. To reduce the attenuation of the quantizer’s input signal due to switched-capacitor (SC) passive summing, the proposed modulator eliminates the
Autor:
Ho-Jin Kim, Kang-Il Cho, Gil-Cho Ahn, Seung-Hoon Lee, Jun-Ho Boo, Yong-Sik Kwak, Jae-Geun Lim
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:1197-1206
This article presents a single-trim switched capacitor (SC) CMOS bandgap reference (BGR) for battery monitoring applications. For a single-temperature trimming, $\beta $ -compensation and curvature correction techniques are employed to minimize non-p
Autor:
Yongchul Jung, Jongho Kim, Mingeon Shin, Haram Ju, Kang-Il Cho, Younghan Lee, Yunho Jung, Sungho Lee
Publikováno v:
2022 IEEE Radar Conference (RadarConf22).
Autor:
Jae-Hyuk Lee, Jun-Sang Park, Gil-Cho Ahn, Je-Min Jeon, Ho-Jin Kim, Kang-Il Cho, Seung-Hoon Lee, Jun-Ho Boo
Publikováno v:
A-SSCC
An ultra-low-power 12-bit 200MS/s two-step pipelined SAR ADC is presented. In the first-stage SAR ADC, a separate DAC is applied with very small unit capacitors which generate the comparator decision threshold, thereby minimizing the required switchi
Autor:
Gil-Cho Ahn, Seung-Hoon Lee, Yong-Sik Kwak, Jun-Sang Park, Jun-Ho Boo, Kang-Il Cho, Ho-Jin Kim
Publikováno v:
A-SSCC
This paper presents a 10-bit 900-MS/s single-channel pipelined successive approximation register (SAR) analog-to-digital converter (ADC). A multiplying digital-to-analog converter (MDAC) using an open-loop amplifier is employed to increase the conver
Autor:
Seung-Hoon Lee, Jae-Geun Lim, Kang-Il Cho, Ho-Jin Kim, Gil-Cho Ahn, Yong-Sik Kwak, Jun-Ho Boo
Publikováno v:
VLSI Circuits
This paper presents a single-trim switched-capacitor (SC) CMOS bandgap reference (BGR) for battery monitoring applications. A β-compensation technique, which is used in conjunction with mismatch averaging, and a discrete time (DT) domain curvature c
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:2772-2782
This paper presents a 2-2 discrete-time (DT) resolution-enhanced sturdy multi-stage noise-shaping (SMASH) delta–sigma modulator. It uses source-follower-based integrators to efficiently increase the operating speed of a DT modulator. A SMASH topolo
Publikováno v:
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE. 17:800-805
Publikováno v:
ISOCC
This paper presents a second-order delta-sigma modulator for audio applications. It uses modified feed-forward (FF) architecture that simplifies the switched-capacitor network of an analog adder in front of the quantizer. The modulator utilizes corre