Zobrazeno 1 - 10
of 76
pro vyhledávání: '"Kanak B. Agarwal"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32:202-215
The use of multiple-patterning (MP) optical lithography for sub-20 nm technologies has inevitably become slow to adopt the next generation of lithography systems. The biggest technical challenge of MP is failure to reach a manufacturable layout-color
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c2c06f61928a419ee1070422c863c830
https://doi.org/10.1109/tcad.2012.2232710
https://doi.org/10.1109/tcad.2012.2232710
Autor:
Yu Gu, Aditya Akella, Kanak B. Agarwal, Wesley M. Felter, John B. Carter, Keqiang He, Eric J. Rozner
Publikováno v:
SIGCOMM
Multi-tenant datacenters are successful because tenants can seamlessly port their applications and services to the cloud. Virtual Machine (VM) technology plays an integral role in this success by enabling a diverse set of software to be run on a unif
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e958b95ab96302f0c7673fb3807b5239
https://doi.org/10.1145/2934872.2934903
https://doi.org/10.1145/2934872.2934903
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29:722-736
Process-induced mechanical stress is used to enhance carrier transport and achieve higher drive currents in current complementary metal-oxide-semiconductor technologies. This paper explores how to fully exploit the layout dependence of stress enhance
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fc9e9eeff8d4ef299aa8c6e8478644ec
https://doi.org/10.1109/tcad.2010.2042893
https://doi.org/10.1109/tcad.2010.2042893
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18:166-170
Increased buffer insertion along on-chip global lines and growing amounts of leakage power have resulted in buffer-based leakage emerging as one of the chief contributors to system leakage power. In this paper, a bus system prototype is implemented i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::18a4d2260f5101f03203a50c7c8d6eb2
https://doi.org/10.1109/tvlsi.2009.2031290
https://doi.org/10.1109/tvlsi.2009.2031290
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 22:12-21
A method for modeling the effects of random process variation through measured transistor current is introduced. The methodology culminates by modeling random current variation at a given operating point above threshold as a zero-mean Additive White
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4e5de6c266a68b7386e74e3aafe34149
https://doi.org/10.1109/tsm.2008.2011630
https://doi.org/10.1109/tsm.2008.2011630
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 22:66-71
We present a technique for fast characterization of the statistical mean and sigma of parametric variations. The technique uses a scan chain to sequentially cycle through a device array, creating a periodic waveform that can be directly measured usin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bf151ceb2758507507f13dbbca18ad48
https://doi.org/10.1109/tsm.2008.2010732
https://doi.org/10.1109/tsm.2008.2010732
Autor:
Kanak B. Agarwal, Dhruva Acharyya, Sani R. Nassif, Frank Liu, Wei Zhao, Yu Cao, Kevin J. Nowka
Publikováno v:
ESSCIRC
Statistical circuit analysis and optimization are critical for robust nanoscale CMOS design. To accurately perform such analysis, primary process variation sources need to be identified and modeled for further circuit simulation. In this work, a rigo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d6d2a7272384c6a7f83c8724a4dacb99
https://doi.org/10.1109/tsm.2008.2011182
https://doi.org/10.1109/tsm.2008.2011182
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 21:526-533
Random microscopic fluctuations in the number and location of dopant atoms can cause a large variation in the threshold voltage (VT) of a MOS device. In this paper, we present a technique for fast characterization of random threshold voltage mismatch
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6c0e42c13f636d3c14fedcad89c4bad6
https://doi.org/10.1109/tsm.2008.2004323
https://doi.org/10.1109/tsm.2008.2004323
Publikováno v:
Integration. 41:319-339
Variation is a significant concern in nanometer-scale CMOS due to manufacturing equipment being pushed to fundamental limits, particularly in lithography. In this paper, we review recent work in coping with variation, through both improved analysis a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::172a9dd5143ce08a38bc2d70fd8172d7
https://doi.org/10.1016/j.vlsi.2007.09.001
https://doi.org/10.1016/j.vlsi.2007.09.001
Autor:
Kanak B. Agarwal, Sani R. Nassif
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16:86-97
The impact of process variation on SRAM yield has become a serious concern in scaled technologies. In this paper, we propose a methodology to analyze the stability of an SRAM cell in the presence of random fluctuations in the device parameters. First
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5f4d78cc67998431f592d46e01cac8ee
https://doi.org/10.1109/tvlsi.2007.909792
https://doi.org/10.1109/tvlsi.2007.909792