Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Kailash Chandrashekar"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:43-54
This article describes a synthesized fractional- $N$ multiplying delay-locked loop (MDLL) implemented in Intel 22-nm FFL FinFET technology. A 2-bit time-period comparator (TPC) is proposed to adjust the ring oscillator frequency to suppress the spurs
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::32c8371c0d0216e758386a527b6e9265
https://doi.org/10.1109/jssc.2020.3021279
https://doi.org/10.1109/jssc.2020.3021279
Publikováno v:
ISLPED
In CPU, SOC, GPU, and PC-on-chip, I/O power consumption can be significant. To improve power efficiency, I/O bundles in group of 4, 8, or 16b, should scale their data rate according to the application requirements. However, clocking architecture impo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6d3245efe375dd59b551b3dcadbc2ce9
https://doi.org/10.1109/islped.2017.8009160
https://doi.org/10.1109/islped.2017.8009160
Autor:
Khoa Minh Nguyen, Muhammad Faisal, Hyung Seok Kim, Satoshi Suzuki, Paolo Madoglio, Amr Fahim, Yorgos Palaskas, Zhichao Zhang, Hongtao Xu, Tan Yulin, Luis Cuellar, Stefano Pellerano, Jianyong Xie, Yanjie Wang, Kailash Chandrashekar, Parmoon Seddighrad, Ashoke Ravi, Divya Shree Vemparala, Thomas A. Tetzlaff, Brent Carlton, William Yee Li, Vaibhav Vaidya
Publikováno v:
ISSCC
To benefit from Moore's law and minimize form-factor and active power consumption, digital-rich SoCs should be integrated in the most advanced technology node. If the transceiver is integrated in a different technology node, multi-chip solutions are
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9beabef6131efd21f56ca0dbb3eb4098
https://doi.org/10.1109/isscc.2017.7870343
https://doi.org/10.1109/isscc.2017.7870343
Autor:
Ashoke Ravi, Carlos Ornelas, D. Shi, Hyung Seok Kim, William Yee Li, Kailash Chandrashekar, Pin-en Su, Paolo Madoglio
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:1721-1729
A 6-bit time-to-digital converter that achieves mismatch free operation by using a single delay cell and sampling flip-flop is presented. The proposed TDC was integrated in a digital fractional-N PLL fabricated in a 32-nm digital SoC CMOS process for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::da0e58be9c6fea450715215d978b1dcf
https://doi.org/10.1109/jssc.2013.2253407
https://doi.org/10.1109/jssc.2013.2253407
Autor:
Ashoke Ravi, Yorgos Palaskas, J. E. Zarate-Roldan, Paolo Madoglio, Kailash Chandrashekar, Hasnain Lakdawala, Stefano Pellerano, Masoud Sajadieh, O. Bochobza-Degani, Hongtao Xu, Luis Cuellar, Marian Verhelst, M. Aguirre-Hernandez
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:3184-3196
A digital outphasing transmitter is presented for 2.4-GHz WiFi. The transmitter consists of two delay-based phase modulators and a 26-dBm integrated switching class-D power amplifier. The delay-based phase modulator delays incoming LO edges with a re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::55fe98dc3b59d7c13317f58cc000e006
https://doi.org/10.1109/jssc.2012.2216671
https://doi.org/10.1109/jssc.2012.2216671
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19:1610-1616
A 10 b opamp-sharing pipeline analog-to-digital (A/D) using current-reuse operational transconductance amplifiers (OTA) with dual nMOS differential inputs is presented. The current-reuse OTA topology facilitates opamp-sharing between all of the conse
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::435696c2c10434e1a005260bc1b35c22
https://doi.org/10.1109/tvlsi.2010.2052376
https://doi.org/10.1109/tvlsi.2010.2052376
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 57:602-606
A reconfigurable 12-b pipeline analog-to-digital converter (ADC) implemented by enabling or disabling MDAC OTAs in parallel is presented. Power scaling is achieved without varying the dc bias conditions of critical analog nodes, reducing design compl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::59c49efb4d884b8828fbf492e5a95991
https://doi.org/10.1109/tcsii.2010.2050948
https://doi.org/10.1109/tcsii.2010.2050948
Publikováno v:
Design, Modeling and Testing of Data Converters ISBN: 9783642396540
The proliferation of portable electronic devices with high data-rate wireless communication capabilities and the increasing emphasis on energy efficiency is continuously applying pressure on the performance and power consumption of ADCs and other mix
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::80af9808d08d1aea2298250eb641ba1c
https://doi.org/10.1007/978-3-642-39655-7_2
https://doi.org/10.1007/978-3-642-39655-7_2
Autor:
Chun Lee, C-T. Fu, Satoshi Suzuki, Duster Jon Sweat, Erkan Alpman, Yorgos Palaskas, Stefano Pellerano, Kailash Chandrashekar, Hasnain Lakdawala, Brent Carlton, Muhammad K. Shafi, Ajay Balankutty, Tan Yulin, Hyung Seok Kim, Ashoke Ravi
Publikováno v:
VLSIC
A 2.4GHz WLAN transceiver is presented with a fully-integrated highly-linear 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC and 320MS/s ADC (high OSR for relaxed filtering), DPLL and fractional LOG, in 32nm CMOS. For 802.11g 54Mbps, without linearization
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::37ccd9245495eb5f8895aaf240e0543c
https://doi.org/10.1109/vlsic.2012.6243797
https://doi.org/10.1109/vlsic.2012.6243797
Publikováno v:
ISSCC
A VCO used in a PLL inside a wireless transceiver can be sensitive to interference from other radio circuitry (e.g. on-chip PA), components of the SoC system (e.g. clocks and their harmonics) and nearby radios. To prevent VCO pulling by the PA, fract
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::18ba2d397a4807b643b9085218bfb3f2
https://doi.org/10.1109/isscc.2012.6177048
https://doi.org/10.1109/isscc.2012.6177048