Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Kai-Yuan Ting"'
Autor:
Wen-Chih Chiou, Calvin Lu, Douglas Yu, C.H. Tsai, Christine Chiu, C. T. Wang, P. K. Huang, Kai-Yuan Ting, Shang-Yun Hou, W. H. Wei, Clark Hu
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
Chip-on-Wafer-on-Substrate with Si interposer (CoWoS-S) is a TSV-based multi-chip integration technology that is widely used in high performance computing (HPC) and artificial intelligence (AI) accelerator area due to its flexibility to accommodate m
Autor:
Douglas Yu, Kai-Yuan Ting, Shang-Yun Hou, C. C. Lin, Wen-Chih Chiou, C.H. Tsai, Feng Wei Kuo, C. T. Wang, H. Hsia
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
One of the prominent challenges for widespread adoption of silicon photonics (SiPh) technology is the availability of an integration platform that can simultaneously meet a wide range of power, performance, and cost criteria in different applications
Autor:
H. Hsia, C. C. Lin, C. T. Wang, C.H. Tsai, Shang-Yun Hou, W. T. Chen, Kai-Yuan Ting, Douglas Yu
Publikováno v:
2020 IEEE 70th Electronic Components and Technology Conference (ECTC).
A logic-HBM2E power delivery system on a chip-on-wafer-on-substrate (CoWoS) platform with a deep trench capacitor (DTC) has been designed and analyzed for high performance computing (HPC) applications. The DTC integrated in the silicon interposer of
Autor:
Alan Roth, Tze-Chiang Huang, Eric Soenen, Charlie Zhou, Sheng-Yao Yang, Mei Wong, Stefan Rusu, Frank Lee, Kai-Yuan Ting, Alex Kalnitsky, Min-Jer Wang, Mark Chen, Ying-Chih Hsu, Kevin Zhang, Paul Ranucci, Ting-Yu Yeh, Hung-Chih Lin, C. H. Kuo, Alvin Leng Sun Loke, J.R. Chu
Publikováno v:
2020 IEEE Symposium on VLSI Technology.
We demonstrate two heterogeneous solutions to improve power delivery to High-Performance Computing (HPC) processors. The scalable HPC vehicle integrates two 7nm CMOS processor chiplets, each with four ARM® Cortex®-A72 cores, that are mounted on a C
Autor:
Chung-Cheng Wu, T.H. Yu, Kai-Yuan Ting, Fang-Cheng Chen, C. T. Wang, C.H. Tsai, Douglas Yu, Shang-Yun Hou, Y.W. Lee, H. Hsia, W. C. Chiou
Publikováno v:
2019 IEEE International Electron Devices Meeting (IEDM).
To accommodate the exceedingly demanding power integrity (PI) requirements for the advanced artificial intelligence (AI) and high performance computing (HPC) components, high-K (HK) based deep trench capacitors (DTC) have been integrated the first ti
Autor:
Victor C. Y. Chang, Kai-Yuan Ting, Shang-Yun Hou, Vincent Wei, T. H. Yu, Doug C. H. Yu, C. T. Wang, Chun-Yu Wu, S. Y. Huang, W. Chris Chen, Clark Hu
Publikováno v:
2017 Symposium on VLSI Technology.
State-of-the-art silicon interposer technology of chip-on-wafer-on-substrate (CoWoS®) has been applied for the first time in fabricating high performance wafer level system-in-package (WLSiP) containing the 2nd-generation high bandwidth memory (HBM2
Autor:
C.Y. Lee, M.C. Chiang, Lin Chih-Yung, Kuei-Shun Chen, V.S. Chang, C.H. Yao, R. Chen, S.M. Jang, R.F. Tsui, C.H. Chang, Y.K. Wu, C.H. Tsai, T. Miyashita, Jhon-Jhy Liaw, Huicheng Chang, Shien-Yang Wu, Joy Cheng, K.H. Pan, Chang-Ta Yang, C. H. Hsieh, Kai-Yuan Ting, Y. Ku
Publikováno v:
2016 IEEE Symposium on VLSI Technology.
For the first time, we demonstrate the smallest, fully functional 32Mb 6-T high density SRAM reported in literature with scaled bulk FinFETs for CMOS technology beyond 10nm node. Scaled FinFET devices exhibit excellent electrostatic with DIBL of
Autor:
Lin Chih-Yung, Tze-Liang Lee, S.Y. Chang, R.F. Tsui, Ming-Huan Tsai, K.H. Pan, Joy Cheng, R. Chen, Kuei-Shun Chen, C.H. Yao, T. Yamamoto, M.C. Chiang, Y.K. Wu, T. Chang, Kai-Yuan Ting, J.H. Chen, Jhon-Jhy Liaw, S. M. Jang, C. H. Lee, S.H. Yang, Y. Ku, H. M. Lee, Vincent S. Chang, Hou-Yu Chen, Liang Min-Chang, H.T. Huang, S.Z. Chang, Yuan-Hung Chiu, Shien-Yang Wu, W. Chang, Chun-Kuang Chen, C.H. Tsai, T. Miyashita, C.H. Chang
Publikováno v:
2014 IEEE International Electron Devices Meeting.
Advancing the state-of-the-art 16nm technology reported last year, an enhanced 16nm CMOS technology featuring the second generation FinFET transistors and advanced Cu/low-k interconnect is presented. Core devices are re-optimized to provide additiona
Autor:
Y. Ku, Y.K. Wu, C.H. Tsai, Tze-Liang Lee, K.H. Pan, T. Miyashita, C.H. Chang, Kuei-Shun Chen, C.H. Yao, Chun-Kuang Chen, C. C. Kuo, S.H. Yang, Jhon-Jhy Liaw, S. M. Jang, Hou-Yu Chen, Liang Min-Chang, W. Chang, H. Y. Chen, R. Chen, H. T. Lin, Chang Chih-Yang, H. M. Lee, Ming-Huan Tsai, M. Yeh, H. M. Lien, H. C. Huang, B. C. Hsu, Joy Cheng, Y. H. Chen, T. Yamamoto, M.C. Chiang, C. C. Liu, J.H. Chen, Yuan-Hung Chiu, Shien-Yang Wu, Y. C. Lu, R.F. Tsui, Lin Chih-Yung, T. Chang, S.Y. Chang, Kai-Yuan Ting, P. R. Chang, Vincent S. Chang
Publikováno v:
2013 IEEE International Electron Devices Meeting.
For the first time, we present a state-of-the-art energy-efficient 16nm technology integrated with FinFET transistors, 0.07um2 high density (HD) SRAM, Cu/low-k interconnect and high density MiM for mobile SoC and computing applications. This technolo