Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Kai D Feng"'
Autor:
Craig Bocash, Ramachandran Muralidhar, Carole D. Graas, Fen Chen, Kai D. Feng, Chad M. Burke, M. Shinosky
Publikováno v:
IRPS
Voltage or Field acceleration model is crucial for low-k TDDB reliability study and lifetime projection. Over the years, many different acceleration models have been proposed based on different physics. In this paper, a method for a relatively fast s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::810de8bebe58be16de807c341d9dc336
https://doi.org/10.1109/irps.2015.7112697
https://doi.org/10.1109/irps.2015.7112697
Autor:
M. Shinosky, Dan Mocuta, Brent A. Anderson, Yun-Yu Wang, F. Chen, John M. Aitken, Kai D. Feng, Steve Mittl, R. Kontra, Ann Swift, Mahender Kumar, Terence Kane, William K. Henson, Yanfeng Wang, Di-an Li, Emily R. Kinser
Publikováno v:
2012 IEEE International Reliability Physics Symposium (IRPS).
The minimum insulator spacing between the polysilicon control gate (PC) and the diffusion contacts (CA) in advanced VLSI circuits is aggressively shrinking due to continuous technology scaling. Meanwhile, rapid adoptions of new materials such as meta
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c10df5d79e192414b38259b2498dd15c
https://doi.org/10.1109/irps.2012.6241865
https://doi.org/10.1109/irps.2012.6241865
Publikováno v:
Applied Physics Letters. 80:3271-3273
This study presents the room-temperature operation of deep-trench type nitride–oxide metal–insulator–semiconductor three-terminal tunneling devices which were fabricated by a standard metal–oxide–semiconductor process. It is instructive to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ffe79bceb3e63d482affcd98c0ce725d
https://doi.org/10.1063/1.1476959
https://doi.org/10.1063/1.1476959
Autor:
Francis F. Szenher, Robert M. Morton, Hanyi Ding, Kai D. Feng, Andrea Paganini, Randall M. Burnett
Publikováno v:
2009 59th Electronic Components and Technology Conference.
The lack of access points to internal circuits can prevent full debug and characterization of highly integrated circuits, such as a receiver or transmitter on a chip. To maximize coverage, prevent costly re-spin and improve time to market, innovative
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::da5f4333436fa358946d1907c7b615d3
https://doi.org/10.1109/ectc.2009.5074104
https://doi.org/10.1109/ectc.2009.5074104
Autor:
Kai D. Feng, A.R. Malladi
Publikováno v:
2007 7th International Conference on ASIC.
The conventional integrated circuit phase locked loop (PLL) has few output signals and offers limited testability. In an event where PLL function does not conform to the specifications, it is often hard and time consuming to debug the problems due to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a803b75675e85d16f5e6e15cf6899d3d
https://doi.org/10.1109/icasic.2007.4415796
https://doi.org/10.1109/icasic.2007.4415796
Autor:
Kai D. Feng
Publikováno v:
2007 7th International Conference on ASIC.
The fractional-N phase lock loop has been widely used in wireless communication systems due to the high frequency resolution and the short locking time. The spur and the phase noise are two main performances of this kind of phase locked loop, but it
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::00e4b91fb61e093c53530ca03845fdda
https://doi.org/10.1109/icasic.2007.4415889
https://doi.org/10.1109/icasic.2007.4415889
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