Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Kai Chung Chang"'
Publikováno v:
Frontiers in Cardiovascular Medicine, Vol 11 (2024)
BackgroundLacosamide is frequently used as a mono- or adjunctive therapy for the treatment of adults with epilepsy. Although lacosamide is known to act on both neuronal and cardiac sodium channels, potentially leading to cardiac arrhythmias, includin
Externí odkaz:
https://doaj.org/article/8606a307d3444e388c792fc3400773cd
Publikováno v:
Journal of Hazardous Materials. 137:1395-1401
The standard sampling methods for toluene diisocyanate (TDI) only collect total TDI without separating the aerosol and gas phases. There are few other samplers, such as the dual filter, triple filter and annular denuder systems (ADS), which are able
Autor:
Chuen Jinn Tsai, C. G. Deshpande, Kuan‐Yu Lin, Hsi‐Chen Lin, Tung Sheng Shih, Kai‐Chung Chang, I-Fu Hung
Publikováno v:
Separation Science and Technology. 41:1799-1812
In order to understand the sampling time effect on the 2,4‐TDI (Toluene diisocyanate) concentrations, laboratory and field tests were conducted in this study. An ADS (annular denuder sampler) and two OFFCs (open face filter holders) with different
Autor:
Kai-Chung Chang, 張凱鈞
95
Adaptive learning is broadly used in agent learning. Cooperation learning is also a crucial ability in multi-agent system to improve the speed of convergence and quality of learning. A flexible also easily approach is needed for agents to lea
Adaptive learning is broadly used in agent learning. Cooperation learning is also a crucial ability in multi-agent system to improve the speed of convergence and quality of learning. A flexible also easily approach is needed for agents to lea
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/53471301474598196356
Autor:
kai-chung-chang, 張凱鈞
92
Face the future chip design, high speed clock signal is the necessary trend. High-speed clock will have smaller margin, because jitter still keeps the variation and clock period is more and more short. In this thesis, We present a clock jitte
Face the future chip design, high speed clock signal is the necessary trend. High-speed clock will have smaller margin, because jitter still keeps the variation and clock period is more and more short. In this thesis, We present a clock jitte
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/31763762251512462034