Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Kai Chong Chan"'
Publikováno v:
2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC).
Autor:
Xuefen Ong, Seung Uk Yoon, Juan Boon Tan, John H. Lau, Yue Ying Ong, Lim Yeow Kheng, Kai Chong Chan, David Yeo, Dong Kyun Sohn, Yanfeng Zhang, Xiaowu Zhang, J. Ong, Soon Wee Ho, Kripesh Vaidyanathan, V. N. Sekhar
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 1:279-290
This paper presents a systematic underfill selection and characterization methods for 21 ×21 mm2 Cu/low-K flip chip packages (65 nm technology) with 150 μm bump pitch. This paper has also correlated the underfill characterization methods with the r
Autor:
Xiaowu Zhang, John H. Lau, David Yeo, Xuefen Ong, Samuel Lim Yak Long, Vempati Srinivasa Rao, Yoon Uk Seung, V. N. Sekhar, Soon Wee Ho, Kripesh Vaidyanathan, Jimmy Ong, Juan Boon Tan, Ming Chinq Jong, Leong Ching Wai, Yue Ying Ong, Kai Chong Chan, Dong Kyun Sohn, Zhang Yanfeng, Y.K. Lim, Vincent Lee Wen Sheng
Publikováno v:
Microelectronics Reliability. 50:986-994
This paper reports the design, assembly and reliability assessment of 21 × 21 mm 2 Cu/low- k flip chip (65 nm node) with 150 μm bump pitch and high bump density. To reduce the stress from the solder bump pad to low- k layers, Metal Redistribution L
Autor:
Yue Ying Ong, Zhong Chen, Juan Boon Tan, Leong Ching Wai, Kai Chong Chan, Soon Wee Ho, Dong Kyun Sohn, David Yeo, Xuefen Ong, Liang Choo Hsia, Y.K. Lim, Kripesh Vaidyanathan
Publikováno v:
Microelectronics Reliability. 49:150-162
A systematic underfill selection approach has been presented to characterize and identify suitable underfill encapsulants for large size flip chip ball grid array (FCBGA) packages. In the selection scheme, a total of six evaluation factors such as fr
Publikováno v:
2012 IEEE 14th Electronics Packaging Technology Conference (EPTC).
Quad flat no-lead (QFN) packages have found wide applications in RF and high-speed digital systems. The purpose of this paper is to study high-frequency performance of conventional low-cost QFN packages, and the impact of various parameters. Physical
Autor:
John H. Lau, Z. Yanfeng, Yue Ying Ong, Xiaowu Zhang, S. W. Ho, Vempati Srinivasa Rao, J. Ong, V. N. Sekhar, Juan Boon Tan, Kai Chong Chan, Dong Kyun Sohn, Vincent Lee Wen Sheng, Y.K. Lim, Leong Ching Wai, Ming Chinq Jong, Xuefen Ong, Yoon Uk Seung, David Yeo, Kripesh Vaidyanathan
Publikováno v:
2008 10th Electronics Packaging Technology Conference.
This paper focused on design, assembly and reliability assessments of 21 × 21 mm2 Cu/Low-K Flip Chip (65 nm technology) with 150 ?m bump pitch. Metal redistribution layer (RDL) and polymer encapsulated dicing lane (PEDL) were applied to the chip waf
Autor:
Yue Ying Ong, Xuefen Ong, Kai Chong Chan, Leong Ching Wai, Dong Kyun Sohn, Y.K. Lim, Soon Wee Ho, Zhong Chen, David Yeo, Liang Choo Hsia, Juan Boon Tan, Kripesh Vaidyanathan
Publikováno v:
2007 9th Electronics Packaging Technology Conference.
In this paper, a systematic underfill selection approach has been presented to characterize and identify favorable underfill encapsulants for 21 times 21 mm2 flip chip ball grid array (FCBGA) package with 150 mum interconnect pitch. A total of six ev
Autor:
Xiaowu Zhang, Y.K. Lim, David Yeo, Juan Boon Tan, Andrew A. O. Tay, J. Ong, V. Kripesh, Liang Choo Hsia, Kai Chong Chan, Dong Kyun Sohn
Publikováno v:
2007 9th Electronics Packaging Technology Conference.
The trend toward finer pitch and higher performance integrated circuits (ICs) devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. However, the low-k materials have lower modulus and poorer adhesion comp
Publikováno v:
2003 International Electronic Packaging Technical Conference and Exhibition, Volume 2.
A solution space design methodology is presented for optimization of off-chip inductors. The analysis has been performed for an advanced wafer level redistribution manufacturing process. Electromagnetic simulations were performed to extract the chara
Publikováno v:
SPIE Proceedings.
Consumers' demand for small, portable, increased functionality, more powerful and lower cost products has been the driving force in the technological advances of electronics packaging. This pushes the trend toward the development of smaller and highe