Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Kah-Hyong Chang"'
Autor:
Xin Zhang, Jianwen Luo, Yat-Hei Lam, Jingjing Lan, Lei Liao, Minkyu Je, Tony Tae-Hyoung Kim, Bo Wang, Wang Ling Goh, Xin Liu, Chao Wang, Jun Zhou, Kah-Hyong Chang, Yongkui Yang
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 62:1149-1153
An energy-efficient sensor node processor (SNP) is presented for intelligent sensing in Internet of Things (IoT) applications. To achieve ultralow energy consumption and satisfying performance, the proposed processor incorporates an ARM Cortex-M0 RIS
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dba845ac6965b13e749f1ec34a4dd618
https://doi.org/10.1109/tcsii.2015.2468927
https://doi.org/10.1109/tcsii.2015.2468927
Publikováno v:
ISIC
This paper presents a 10-bit, 5.12 kS/s noise-shaping non-binary successive approximation ADC (SAR ADC). The proposed noise-shaping SAR ADC requires an additional capacitor and a buffer along with a non-binary SAR ADC to implement the first order noi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::15678c0f6e31f914159e607ad73d4d2e
https://doi.org/10.1109/isicir.2016.7829678
https://doi.org/10.1109/isicir.2016.7829678
Autor:
Kah-Hyong Chang, Raveendran Paramesran
Publikováno v:
Journal of Signal Processing Systems. 78:179-186
In this paper, we present a single-chip architecture for generating a full set of geometric moments using digital filters. Other types of moments such as Zernike and Tchebichef moments can also be implemented. The architecture can be configured for a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::714ea756b7cab91e1055029bab44a70c
https://doi.org/10.1007/s11265-013-0857-9
https://doi.org/10.1007/s11265-013-0857-9
Autor:
Kah-Hyong Chang, Xin Liu, Jia Hao Cheong, Saisundar Sankaranarayanan, Dexing Pang, Hongzhao Zheng
A digital baseband Application-Specific Integrated Circuit (ASIC) (yclic Redundancy Checkis developed for a microchip transponder to transmit signals and temperature levels from biomedical monitoring devices. The transmission protocol is adapted from
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::720532fdd108f52e9bdcfd00790c5eba
Publikováno v:
IEEE Transactions on Circuits and Systems for Video Technology. 22:414-425
Moments extraction from high resolution images in real time may require a large amount of hardware resources. Using a direct method may involve a critically high operating frequency. This paper presents two improved digital-filter based moment accele
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e52367a51c705ad251fcafacd6c03706
https://doi.org/10.1109/tcsvt.2011.2163980
https://doi.org/10.1109/tcsvt.2011.2163980
Autor:
Kah-Hyong Chang, Jianwen Luo, Xin Zhang, Bo Wang, Minkyu Je, Yongkui Yang, Tony Tae-Hyoung Kim, Jun Zhou, Yat-Hei Lam, Lei Liao, Xin Liu, Jingjing Lan, Chao Wang, Wang Ling Goh
Publikováno v:
2014 International SoC Design Conference (ISOCC).
This paper presents a sensor node processor (SNP) with optimized energy efficiency and performance for intelligent sensing through architecture-level optimization and ultra-low voltage operation with timing-error monitoring. Two typical intelligent s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ead7c274cb5236e22d7fd72305e574f5
https://doi.org/10.1109/isocc.2014.7087600
https://doi.org/10.1109/isocc.2014.7087600
Publikováno v:
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).
This paper presents a 16-transistor charge-pumped DFF featuring a low energy-delay product for near-/sub-threshold applications. The device count of the proposed DFF is minimized by eliminating clock buffer and employing pass gates instead of transmi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5a184b155eb3d3367990c90aff9a708e
https://doi.org/10.1109/asscc.2013.6690997
https://doi.org/10.1109/asscc.2013.6690997
Publikováno v:
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).
A new in-situ timing-error prediction and prevention technique named HEPP is proposed for mitigating the impact of PVT variations on ultra-low-voltage digital designs. Compared to the prior techniques including Razor and Canary flip-flop, the propose
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c2cc2ebb4ffe26e337005c62f2f086eb
https://doi.org/10.1109/asscc.2013.6690999
https://doi.org/10.1109/asscc.2013.6690999
Autor:
Zhou, Jun, Xin Liu, Chao Wang, Kah-Hyong Chang, Jianwen Luo, Jingjing Lan, Lei Liao, Yat-Hei Lam, Yongkui Yang, Bo Wang, Xin Zhang, Wang Ling Goh, Tony Tae-Hyoung Kim, Minkyu Je
Publikováno v:
2014 International SoC Design Conference (ISOCC); 2014, p70-71, 2p