Zobrazeno 1 - 10
of 21
pro vyhledávání: '"Kadiyala, Rao"'
Publikováno v:
Journal of Electronic Testing. 30:125-147
Power-supply noise is one of the major contributing factor for yield loss in sub-micron designs. Excessive switching in test mode causes supply voltage to droop more than in functional mode leading to failures in delay tests that would not occur othe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bee346a563d642338c5f6510d681fc0d
https://doi.org/10.1007/s10836-013-5425-5
https://doi.org/10.1007/s10836-013-5425-5
Publikováno v:
VDAT
This paper continues to build on the dynamic current transient estimation method introduced in previous work. Our previously introduced method uses pre-characterized data from standard cells to estimate the total current transient of a path. This met
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e64233d6cb7a9107d1f667b4228af1fa
https://doi.org/10.1109/isvdat.2015.7208110
https://doi.org/10.1109/isvdat.2015.7208110
Publikováno v:
HOST
Two major security challenges for integrated circuits (IC) that involve encryption cores are side-channel based attacks and malicious hardware insertions (trojans). Side-channel attacks predominantly use power supply measurements to exploit the corre
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d180d1a992e4379e1994eaf706c53430
https://doi.org/10.1109/hst.2015.7140244
https://doi.org/10.1109/hst.2015.7140244
Publikováno v:
VTS
Variations in the power-distribution network are exacerbated because of scaled supply voltages and smaller noise margins in sub-nanometer designs, which adversely affect performance and yield. Power-Supply noise incurred by excessive simultaneous swi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f57db53572d10fbe7de77df8a7f17ec6
https://doi.org/10.1109/vts.2015.7116293
https://doi.org/10.1109/vts.2015.7116293
Autor:
Sushmita Kadiyala Rao, Ryan Robucci, Michael Skaggs, Chintan Patel, Nilanjan Banerjee, Bharath Shivashankar
Publikováno v:
LATS
Power supply noise is a critical issue in transition and delay testing. As compared to functional operations, test vectors induce increased switching. This escalation in switching contributes to an increase in power supply noise which, in turn, cause
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f0876651d7c8ffca6766afdec3a34cb4
https://doi.org/10.1109/latw.2015.7102520
https://doi.org/10.1109/latw.2015.7102520
Autor:
Kadiyala Rao, Sushmita
Power-supply noise is a major contributing factor for yield loss in sub-micron designs. Excessive switching in test mode causes supply voltage to droop more than in functional mode, leading to failures in delay tests that would not occur otherwise un
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e79dda2d667eba96ce2ca093c858d211
Publikováno v:
DFTS
Supply noise is a contributing factor for yield loss that has to be taken into account when designing fault tolerant systems. Extensive logic switching in today's circuits cause this supply noise that results in increase in path delays that can fail
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7ac1fe0ad88978c8ef493dda3be31749
https://doi.org/10.1109/dft.2013.6653618
https://doi.org/10.1109/dft.2013.6653618
Publikováno v:
VTS
Most existing techniques and tools predict static IR-drop, which accounts for only part of the total voltage drop on the power grid. We present a scalable current-based dynamic method to estimate both IR and Ldi/dt drop caused by simultaneous switchi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::69893a11c906f1566023417fddfa3453
https://doi.org/10.1109/vts.2013.6548903
https://doi.org/10.1109/vts.2013.6548903
Publikováno v:
VTS
Power Supply Noise has a significant impact on path delay and therefore its estimation is critical in delay testing. In deep sub-micron technologies, voltages are scaled and the number of switching gates has increased which make chips susceptible to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2a37bf70a35e190cae42686e51f50f9e
https://doi.org/10.1109/vts.2012.6231066
https://doi.org/10.1109/vts.2012.6231066
Autor:
Kadiyala Rao, Sushmita
Circuit Simulation has long been a dependable technique for design engineers for functional testing before a circuit is taken to silicon. But as we move into deep sub-micron technologies, chips are becoming more complex and denser. The dense power gr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::75c1b73699deb206fa87ec8fa4874f0f