Zobrazeno 1 - 10
of 60
pro vyhledávání: '"KANELLOPOULOS KONSTANTINOS"'
Autor:
Bera, Rahul, Ranganathan, Adithya, Rakshit, Joydeep, Mahto, Sujit, Nori, Anant V., Gaur, Jayesh, Olgun, Ataberk, Kanellopoulos, Konstantinos, Sadrosadati, Mohammad, Subramoney, Sreenivas, Mutlu, Onur
Load instructions often limit instruction-level parallelism (ILP) in modern processors due to data and resource dependences they cause. Prior techniques like Load Value Prediction (LVP) and Memory Renaming (MRN) mitigate load data dependence by predi
Externí odkaz:
http://arxiv.org/abs/2406.18786
Autor:
Canpolat, Oğuzhan, Yağlıkçı, A. Giray, Olgun, Ataberk, Yüksel, İsmail Emir, Tuğrul, Yahya Can, Kanellopoulos, Konstantinos, Ergin, Oğuz, Mutlu, Onur
RowHammer is a major read disturbance mechanism in DRAM where repeatedly accessing (hammering) a row of DRAM cells (DRAM row) induces bitflips in other physically nearby DRAM rows. RowHammer solutions perform preventive actions (e.g., refresh neighbo
Externí odkaz:
http://arxiv.org/abs/2404.13477
Autor:
Kanellopoulos, Konstantinos, Bostanci, F. Nisa, Olgun, Ataberk, Yaglikci, A. Giray, Yuksel, Ismail Emir, Ghiasi, Nika Mansouri, Bingol, Zulal, Sadrosadati, Mohammad, Mutlu, Onur
The adoption of processing-in-memory (PiM) architectures has been gaining momentum because they provide high performance and low energy consumption by alleviating the data movement bottleneck. Yet, the security of such architectures has not been thor
Externí odkaz:
http://arxiv.org/abs/2404.11284
Virtuoso: An Open-Source, Comprehensive and Modular Simulation Framework for Virtual Memory Research
Virtual memory is a cornerstone of modern computing systems.Introduced as one of the earliest instances of hardware-software co-design, VM facilitates programmer-transparent memory man agement, data sharing, process isolation and memory protection. E
Externí odkaz:
http://arxiv.org/abs/2403.04635
Autor:
Bostanci, F. Nisa, Yuksel, Ismail Emir, Olgun, Ataberk, Kanellopoulos, Konstantinos, Tugrul, Yahya Can, Yaglikci, A. Giray, Sadrosadati, Mohammad, Mutlu, Onur
We propose a new RowHammer mitigation mechanism, CoMeT, that prevents RowHammer bitflips with low area, performance, and energy costs in DRAM-based systems at very low RowHammer thresholds. The key idea of CoMeT is to use low-cost and scalable hash-b
Externí odkaz:
http://arxiv.org/abs/2402.18769
Autor:
Kanellopoulos, Konstantinos, Nam, Hong Chul, Bostanci, F. Nisa, Bera, Rahul, Sadrosadati, Mohammad, Kumar, Rakesh, Bartolini, Davide-Basilio, Mutlu, Onur
Address translation is a performance bottleneck in data-intensive workloads due to large datasets and irregular access patterns that lead to frequent high-latency page table walks (PTWs). PTWs can be reduced by using (i) large hardware TLBs or (ii) l
Externí odkaz:
http://arxiv.org/abs/2310.04158
Computing on encrypted data is a promising approach to reduce data security and privacy risks, with homomorphic encryption serving as a facilitator in achieving this goal. In this work, we accelerate homomorphic operations using the Processing-in- Me
Externí odkaz:
http://arxiv.org/abs/2309.06545
Autor:
Ghiasi, Nika Mansouri, Vijaykumar, Nandita, Oliveira, Geraldo F., Orosa, Lois, Fernandez, Ivan, Sadrosadati, Mohammad, Kanellopoulos, Konstantinos, Hajinazar, Nastaran, Luna, Juan Gómez, Mutlu, Onur
Partitioning applications between NDP and host CPU cores causes inter-segment data movement overhead, which is caused by moving data generated from one segment (e.g., instructions, functions) and used in consecutive segments. Prior works take two app
Externí odkaz:
http://arxiv.org/abs/2212.06292
Autor:
Kanellopoulos, Konstantinos, Bera, Rahul, Stojiljkovic, Kosta, Bostanci, Nisa, Firtina, Can, Ausavarungnirun, Rachata, Kumar, Rakesh, Hajinazar, Nastaran, Sadrosadati, Mohammad, Vijaykumar, Nandita, Mutlu, Onur
Conventional virtual memory (VM) frameworks enable a virtual address to flexibly map to any physical address. This flexibility necessitates large data structures to store virtual-to-physical mappings, which leads to high address translation latency a
Externí odkaz:
http://arxiv.org/abs/2211.12205
Autor:
Ghiasi, Nika Mansouri, Sadrosadati, Mohammad, Oliveira, Geraldo F., Kanellopoulos, Konstantinos, Ausavarungnirun, Rachata, Luna, Juan Gómez, Manglik, Aditya, Ferreira, João, Kim, Jeremie S., Giannoula, Christina, Vijaykumar, Nandita, Park, Jisung, Mutlu, Onur
Recent nano-technological advances enable the Monolithic 3D (M3D) integration of multiple memory and logic layers in a single chip with fine-grained connections. M3D technology leads to significantly higher main memory bandwidth and shorter latency t
Externí odkaz:
http://arxiv.org/abs/2210.08508