Zobrazeno 1 - 10
of 49
pro vyhledávání: '"K.R. Mistry"'
Autor:
L.A. Bair, R. Flatley, D.A. Antoniadis, G.J. Grula, K.R. Mistry, Jeffrey W. Sleight, B. Miner
Publikováno v:
IEEE Transactions on Electron Devices. 46:2201-2209
An in-depth analysis of the role of parasitic bipolar gain reduction in 0.25-/spl mu/m partially depleted SOI MOSFETs is presented, considering both dc characteristics as well as circuit operation. The effect of channel doping, silicide proximity, an
Publikováno v:
IEEE Transactions on Electron Devices. 42:116-122
The effect of hot carrier stress on surface channel p-MOS transistors is examined for two different oxide thicknesses. It is shown that the hot carrier failure time increases by 4 orders of magnitude when the oxide thickness is reduced from 10.7 nm t
Publikováno v:
IEEE Transactions on Electron Devices. 40:1284-1295
Reviews present understanding of the AC stress effect in n-MOSFETs, defining and parameterizing the AC stress model. The authors incorporate the AC hot-carrier model into a circuit-level hot-carrier reliability simulator, ADHOC, that works in concert
Publikováno v:
IEEE Transactions on Electron Devices. 40:980-985
Damage to n-channel MOSFETs under different levels of drain current stress is compared. It is shown that the post-stress I/sub d/-V/sub gs/ characteristics show distinctly different behavior for different stresses. These differences are interpreted i
Autor:
B.S. Doyle, K.R. Mistry
Publikováno v:
IEEE Transactions on Electron Devices. 40:152-156
Damage in surface channel p-MOS transistors arising from hot-carrier stress is examined using a recently proposed lifetime extraction method. It is shown that the p-MOS behavior with respect to hot-carrier stress runs counter to that of n-MOS transis
Autor:
K.R. Mistry, B. Doyle
Publikováno v:
IEEE Transactions on Electron Devices. 40:96-104
The origins of the enhanced AC hot-carrier stress damage are examined. The enhancement in hot-carrier stress damage under AC stress conditions observed with respect to damage under DC stress conditions can fully be explained by the presence of three
Publikováno v:
IEEE Transactions on Electron Devices. 39:2290-2297
The effect of junction engineering on the hot carrier lifetimes of p-MOS transistors is examined. A normalizing method for predicting lifetimes is developed and used to show that a critical parameter controlling the lifetimes of submicrometer p-MOS d
Autor:
B.S. Doyle, K.R. Mistry
Publikováno v:
IEEE Transactions on Electron Devices. 37:1301-1307
Hot carrier degradation of p-MOS devices at low gate voltages (V/sub g/
Publikováno v:
IEEE Electron Device Letters. 19:499-501
A technique for characterizing the effectiveness of SOI MOSFET body contacts under transient conditions, by measuring the transient lateral bipolar current in a SOI pass gate, is demonstrated. Using this technique, the minimum rise or fall edge rate
Publikováno v:
IEEE Electron Device Letters. 18:51-53
The origins of the different power laws arising from hot carrier stressing at low and high gate voltages are examined. It is found that damage at V/sub g/=V/sub d/ (predominantly electron trapping in the oxide) has the same underlying 0.5 power law e