Zobrazeno 1 - 10
of 23
pro vyhledávání: '"K.K. Duganapalli"'
Publikováno v:
Integration. 41:27-37
The manufacturing defect in the interconnect lines can lead to various electrical faults, e.g. defect due to under-etching effect/conductive particle contamination on interconnect line can lead to increased coupling capacitances between the two adjac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::55d6a2c095aa9da8ff53bdc36a873d06
https://doi.org/10.1016/j.vlsi.2007.04.005
https://doi.org/10.1016/j.vlsi.2007.04.005
Publikováno v:
DDECS
The coupling noise between adjacent interconnects has become major SI issue, due to higher aspect ratios of interconnects in DSM chips, giving rise to cross talk failures. The Genetic Algorithms (GA) have been applied earlier in different engineering
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f6502192d2adac290e7e1d50c648a139
https://doi.org/10.1109/ddecs.2015.34
https://doi.org/10.1109/ddecs.2015.34
Autor:
Dorota Kubalińska, Angelika Bunse-Gerstner, Rainer Laur, K.K. Duganapalli, Shyam Praveen Vudathu
Publikováno v:
Microsystem Technologies. 13:1545-1551
This paper presents an emerging theory on the effects of unavoidable process variations during the fabrication of MEMS and other microsystems. The effects of parametric variations on device performance and design yield of the microsystems devices are
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::336aa6497967ac6d5002606ed705d01e
https://doi.org/10.1007/s00542-006-0263-3
https://doi.org/10.1007/s00542-006-0263-3
Publikováno v:
2008 2nd Electronics Systemintegration Technology Conference.
Noise effects in coupled interconnects, i.e. crosstalk induced glitch and crosstalk induced delay can significantly impact the performance of deep sub-micron (DSM) chips. Therefore, in this paper distributed RLGC transient model of coupled interconne
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::174514321544e1416998c4ab0c7d829d
https://doi.org/10.1109/estc.2008.4684517
https://doi.org/10.1109/estc.2008.4684517
Publikováno v:
2008 2nd Electronics Systemintegration Technology Conference.
Nowadays, aggressive scaling of transistor dimensions has led to the reduction of process geometries and thereby higher device density in DSM chips. Higher signal switching speeds and increased aspect ratios of interconnects in chips has enforced the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1939756d8acf0da4144f146c48d002d1
https://doi.org/10.1109/estc.2008.4684381
https://doi.org/10.1109/estc.2008.4684381
Autor:
Rainer Laur, D. Westphal, K. Zielinski, K.K. Duganapalli, A.K. Palit, Dobrivoje Popovic, W. Anheier
Publikováno v:
Studies in Computational Intelligence ISBN: 9783540762850
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cf4c1b2bf55e061e3a8e3f014272d91e
https://doi.org/10.1007/978-3-540-76286-7_13
https://doi.org/10.1007/978-3-540-76286-7_13
Publikováno v:
2007 9th Electronics Packaging Technology Conference.
Interconnects being the limiting factor for both performance and density in today's VLSI systems, interconnect parasitics are considered to be the prime sources of signal integrity problems. Line inductance and/or mutual inductance in certain interco
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::56e0c64eecd07a8a4c6437bcee8a8696
https://doi.org/10.1109/eptc.2007.4469748
https://doi.org/10.1109/eptc.2007.4469748
Publikováno v:
DDECS
The paper presents an efficient crosstalk simulator tool "XSIM" and it's methodology for analysis and modeling of signal integrity faults in deep sub-micron chips. The tool is used for analyzing the crosstalk coupling behavior in both defective and d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::75798c59adc7b476f70584d10a154e23
https://doi.org/10.1109/ddecs.2007.4295274
https://doi.org/10.1109/ddecs.2007.4295274
Publikováno v:
Journal of Circuits, Systems and Computers. 25:1640018
With the shrinking feature size and increasing aspect ratios of interconnects in DSM chips, the coupling noise between adjacent interconnects has become a major signal integrity (SI) issue, giving rise to crosstalk failures. In older technologies, SI
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6231f59f5a0b0b82b2e9fe318dde7975
https://doi.org/10.1142/s0218126616400181
https://doi.org/10.1142/s0218126616400181
Publikováno v:
DFT
The paper addresses here the fault model of particular type of manufacturing defects in the metal layers of deep sub-micron (DSM) chips, e.g. conductive particle contamination, bad handling or under-etching defects in the pair of parallel interconnec
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2fd2019a5136a837b26a429aa843f70e
https://doi.org/10.1109/dft.2006.36
https://doi.org/10.1109/dft.2006.36