Zobrazeno 1 - 10
of 37
pro vyhledávání: '"K.E. Grosspietsch"'
Publikováno v:
IEEE Micro. 21:12-15
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e446b57c1129ff08b9a7df639d70e5f7
https://doi.org/10.1109/mm.2001.958695
https://doi.org/10.1109/mm.2001.958695
Publikováno v:
IEEE Micro. 18:8-11
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c6a70f7a2b19456df12529f446f3d11a
https://doi.org/10.1109/mm.1998.735939
https://doi.org/10.1109/mm.1998.735939
Autor:
K.E. Grosspietsch
Publikováno v:
IEEE Micro. 14:60-68
As the demand for highly parallel systems grows, the vast amount of concurrently operating hardware involved can make it difficult to guarantee proper system behavior. Problems arise both from permanent and transient hardware faults and from errors c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::33bc060266229a1ebc3567900f64da3e
https://doi.org/10.1109/40.259902
https://doi.org/10.1109/40.259902
Autor:
K.E. Grosspietsch, R. Reetz
Publikováno v:
IEEE Micro. 12:58-67
The basic features of a content-addressable processor/register array (CAPRA) are discussed. The features are the inclusion of logic elements directly within the word cells or bit cells of memory, use of a maskable decoder to enable multiaccess to the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d2cb5d66d99351c20424185ee50f101c
https://doi.org/10.1109/40.180248
https://doi.org/10.1109/40.180248
Autor:
K.E. Grosspietsch
Publikováno v:
IEEE Micro. 12:12-19
The functional structure of a classical content-addressable memory (CAM) and its realization at the transistor level are described. Some unorthodox CAM approaches are briefly examined. Associative processor systems are discussed, and application-spec
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9bdc8a7efa112f309f87b7e9962ae0c7
https://doi.org/10.1109/40.141599
https://doi.org/10.1109/40.141599
Publikováno v:
Microprocessing and Microprogramming. 32:335-341
An innovative concept for parallel image sensing and preprocessing as an interface to artificial neural networks is presented: The architecture is based on a parallel preprocessor system, integrated sensor elements, and readout electronics on a singl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::760f93ae2cbd4f96b378482322518bf4
https://doi.org/10.1016/0165-6074(91)90367-3
https://doi.org/10.1016/0165-6074(91)90367-3
Publikováno v:
[1991] Proceedings, Advanced Computer Technology, Reliable Systems and Applications.
Problems of fault detection and fault tolerance for an innovative special associative memory architecture, the associative RAM (ARAM), are considered. Additional components to solve these problems are presented. The resulting reliability improvement
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::100e16b1c36959b9dbd8fac8c832390e
https://doi.org/10.1109/cmpeur.1991.257473
https://doi.org/10.1109/cmpeur.1991.257473
Autor:
A. Romanovsky, K.E. Grosspietsch
Publikováno v:
EUROMICRO
In this paper a concept is described to further improve the dependability characteristics of n-version systems. As one part of this strategy, we introduce an adaptive version management scheme. It is based on the use of dynamically changeable weight
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::93c6604a62bb2fb7deca18749fac7efc
https://doi.org/10.1109/eurmic.2001.952453
https://doi.org/10.1109/eurmic.2001.952453
Autor:
K.E. Grosspietsch
Publikováno v:
IPDPS
In this paper a component-based approach for implementing n-version software systems is prresented. For each of the system modules, a set of diversely developed module candidates is considered. It is demonstrated that in general such a modular constr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1bea68795810bcf446742a72d73178e5
https://doi.org/10.1109/ipdps.2002.1016526
https://doi.org/10.1109/ipdps.2002.1016526
Autor:
J. Buddefeld, K.E. Grosspietsch
Execution of artificial neural networks, especially for online pattern recognition, mainly depends on time-efficient execution of weighted sums. A new architecture achieves this goal, with a computation time superior to the time complexity of sequent
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::23f43735657ab00ec6dd3f3ba0ec27df
https://publica.fraunhofer.de/handle/publica/202948
https://publica.fraunhofer.de/handle/publica/202948
