Zobrazeno 1 - 10
of 59
pro vyhledávání: '"K.D. Buddharaju"'
Publikováno v:
Advanced Engineering Materials. 16:1032-1037
The growth mechanism of Ni-germanosilicide in Si0.5Ge0.5 NW with and without silicon dioxide shell encapsulation was investigated using transmission electron microscope imaging with in situ annealing of SiGe NW array samples capped with Ni. At 200 an
Publikováno v:
Journal of Electronic Materials. 42:1476-1481
Contact resistance gains prominence as feature size reduces to the nanometer length scale. This work studies the effects of electrical contact resistance on the performance of silicon nanowire-based thermoelectric coolers using COMSOL Multiphysics. T
Publikováno v:
Journal of Electronic Materials. 41:989-992
A silicon nanowire (SiNW) array-based thermoelectric generator (TEG) was assembled and characterized. The SiNW array had pitch of 400 nm, and SiNW diameter and height of
Autor:
Dim-Lee Kwong, G. Q. Lo, S.C. Rustagi, K.D. Buddharaju, Sukant K. Tripathy, Navab Singh, Subramanian Balakumar, B. Tan, Rajesh Kumar
Publikováno v:
Journal of Electronic Materials. 38:443-448
In this study, the authors report on the fabrication of Ge-rich SiGe nanowires (SGNWs) by oxidation of SiGe fins on insulator. Nanowires of different shapes and size are obtained by varying the initial fin shape, Ge content, oxidation process tempera
Autor:
K.D. Buddharaju, N. Balasubramanian, Sanjeev Kumar Manhas, Ajay Agarwal, Dim-Lee Kwong, S.C. Rustagi, Navab Singh, Guo-Qiang Lo
Publikováno v:
IEEE Transactions on Electron Devices. 55:3107-3118
Nanowire (NW) devices, particularly the gate-all-around (GAA) CMOS architecture, have emerged as the front-runner for pushing CMOS scaling beyond the roadmap. These devices offer unique advantages over their planar counterparts which make them feasib
Autor:
J. Fu, N. Balasubramanian, Sanjeev Kumar Manhas, Ajay Agarwal, Subramanian Balakumar, Z. Hui, Dim-Lee Kwong, Navab Singh, Subhash C. Rustogi, Guo-Qiang Lo, K.D. Buddharaju
Publikováno v:
ECS Transactions. 13:201-211
For the end of the roadmap CMOS scaling, the non-classical device architecture, Gate All Around (GAA) FET with nanowire (NW) channel body offers the ultimate electro-static control and thus has the potential to push the gate length to few nanometers.
Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach
Autor:
K.D. Buddharaju, Selin H. G. Teo, Navab Singh, N. Balasubramanian, S.C. Rustagi, Dim-Lee Kwong, Guo-Qiang Lo
Publikováno v:
Solid-State Electronics. 52:1312-1317
We present the monolithic integration of gate-all-around (GAA) Si-nanowire FETs into CMOS logic using top-down approach. Inverters are chosen as the test vehicles for demonstration. Empirically optimized designs show sharp ON–OFF transitions with h
Publikováno v:
IEEE Electron Device Letters. 29:791-794
This letter presents a vertical gate-all-around silicon nanowire transistor on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio (up to 50: 1) vertical nanowires with diameter ~20 nm are achieved from lithography and dr
Autor:
She Mein Wong, Ajay Agarwal, K.D. Buddharaju, Ru-Ern Chee, Jay Huiyi Chua, N. Balasubramanian, Guo-Jun Zhang
Publikováno v:
Biosensors and Bioelectronics. 23:1701-1707
The highly sensitive and sequence-specific detection of single-stranded oligonucleotides using nonoxidized silicon nanowires (SiNWs) is demonstrated. To maximize device sensitivity, the surface of the SiNWs was functionalized with a densely packed or
Autor:
N. Balasubramanian, K.D. Buddharaju, Dim-Lee Kwong, S. R. Omampuliyur, C.H. Tung, Selin H. G. Teo, Navab Singh, Guo-Qiang Lo, Wei-Wei Fang, S.C. Rustagi
Publikováno v:
IEEE Electron Device Letters. 28:1021-1024
This letter demonstrates, for the first time, the integration of gate-all-around (GAA) Si-nanowire transistors into CMOS inverters using top-down approach. With matching of the drive currents of n- and p-MOSFETs using different gate lengths to achiev