Zobrazeno 1 - 10
of 87
pro vyhledávání: '"K.D. Buddharaju"'
Publikováno v:
Advanced Engineering Materials. 16:1032-1037
The growth mechanism of Ni-germanosilicide in Si0.5Ge0.5 NW with and without silicon dioxide shell encapsulation was investigated using transmission electron microscope imaging with in situ annealing of SiGe NW array samples capped with Ni. At 200 an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6a3f52abf55faf7a4bc3657bb6ef7c19
https://doi.org/10.1002/adem.201300462
https://doi.org/10.1002/adem.201300462
Publikováno v:
Journal of Electronic Materials. 42:1476-1481
Contact resistance gains prominence as feature size reduces to the nanometer length scale. This work studies the effects of electrical contact resistance on the performance of silicon nanowire-based thermoelectric coolers using COMSOL Multiphysics. T
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::af9d2fabf51ae138e8bc93ea6cad9c45
https://doi.org/10.1007/s11664-012-2294-0
https://doi.org/10.1007/s11664-012-2294-0
Publikováno v:
Journal of Electronic Materials. 41:989-992
A silicon nanowire (SiNW) array-based thermoelectric generator (TEG) was assembled and characterized. The SiNW array had pitch of 400 nm, and SiNW diameter and height of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::05b3757c862dc3a53a3da5ac6ea52820
https://doi.org/10.1007/s11664-012-1901-4
https://doi.org/10.1007/s11664-012-1901-4
Autor:
Dim-Lee Kwong, G. Q. Lo, S.C. Rustagi, K.D. Buddharaju, Sukant K. Tripathy, Navab Singh, Subramanian Balakumar, B. Tan, Rajesh Kumar
Publikováno v:
Journal of Electronic Materials. 38:443-448
In this study, the authors report on the fabrication of Ge-rich SiGe nanowires (SGNWs) by oxidation of SiGe fins on insulator. Nanowires of different shapes and size are obtained by varying the initial fin shape, Ge content, oxidation process tempera
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b1b36f558e912b4f9d7a60901edf2c58
https://doi.org/10.1007/s11664-008-0621-2
https://doi.org/10.1007/s11664-008-0621-2
Autor:
K.D. Buddharaju, N. Balasubramanian, Sanjeev Kumar Manhas, Ajay Agarwal, Dim-Lee Kwong, S.C. Rustagi, Navab Singh, Guo-Qiang Lo
Publikováno v:
IEEE Transactions on Electron Devices. 55:3107-3118
Nanowire (NW) devices, particularly the gate-all-around (GAA) CMOS architecture, have emerged as the front-runner for pushing CMOS scaling beyond the roadmap. These devices offer unique advantages over their planar counterparts which make them feasib
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8eabb2132dbfb6017527afa680dda119
https://doi.org/10.1109/ted.2008.2005154
https://doi.org/10.1109/ted.2008.2005154
Autor:
J. Fu, N. Balasubramanian, Sanjeev Kumar Manhas, Ajay Agarwal, Subramanian Balakumar, Z. Hui, Dim-Lee Kwong, Navab Singh, Subhash C. Rustogi, Guo-Qiang Lo, K.D. Buddharaju
Publikováno v:
ECS Transactions. 13:201-211
For the end of the roadmap CMOS scaling, the non-classical device architecture, Gate All Around (GAA) FET with nanowire (NW) channel body offers the ultimate electro-static control and thus has the potential to push the gate length to few nanometers.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dff407022fad81dd3280f9385a41b816
https://doi.org/10.1149/1.2911501
https://doi.org/10.1149/1.2911501
Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach
Autor:
K.D. Buddharaju, Selin H. G. Teo, Navab Singh, N. Balasubramanian, S.C. Rustagi, Dim-Lee Kwong, Guo-Qiang Lo
Publikováno v:
Solid-State Electronics. 52:1312-1317
We present the monolithic integration of gate-all-around (GAA) Si-nanowire FETs into CMOS logic using top-down approach. Inverters are chosen as the test vehicles for demonstration. Empirically optimized designs show sharp ON–OFF transitions with h
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9875e18b5d24c5fc45f0f3742a23c69f
https://doi.org/10.1016/j.sse.2008.04.017
https://doi.org/10.1016/j.sse.2008.04.017
Publikováno v:
IEEE Electron Device Letters. 29:791-794
This letter presents a vertical gate-all-around silicon nanowire transistor on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio (up to 50: 1) vertical nanowires with diameter ~20 nm are achieved from lithography and dr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e80a7da698ea5132366cd903a344ed93
https://doi.org/10.1109/led.2008.2000617
https://doi.org/10.1109/led.2008.2000617
Autor:
She Mein Wong, Ajay Agarwal, K.D. Buddharaju, Ru-Ern Chee, Jay Huiyi Chua, N. Balasubramanian, Guo-Jun Zhang
Publikováno v:
Biosensors and Bioelectronics. 23:1701-1707
The highly sensitive and sequence-specific detection of single-stranded oligonucleotides using nonoxidized silicon nanowires (SiNWs) is demonstrated. To maximize device sensitivity, the surface of the SiNWs was functionalized with a densely packed or
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c3835ec82dc9ce130656c337a5318863
https://doi.org/10.1016/j.bios.2008.02.006
https://doi.org/10.1016/j.bios.2008.02.006
Autor:
N. Balasubramanian, K.D. Buddharaju, Dim-Lee Kwong, S. R. Omampuliyur, C.H. Tung, Selin H. G. Teo, Navab Singh, Guo-Qiang Lo, Wei-Wei Fang, S.C. Rustagi
Publikováno v:
IEEE Electron Device Letters. 28:1021-1024
This letter demonstrates, for the first time, the integration of gate-all-around (GAA) Si-nanowire transistors into CMOS inverters using top-down approach. With matching of the drive currents of n- and p-MOSFETs using different gate lengths to achiev
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::22bacd250e997856af6aeca69b4e33b6
https://doi.org/10.1109/led.2007.906622
https://doi.org/10.1109/led.2007.906622