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pro vyhledávání: '"K. Verhaege"'
Akademický článek
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Autor:
Cong-Son Trinh, Phillip Czeslaw Jozwiak, Cornelius Christian Russ, Markus Paul Josef Mergens, John Armer, Russell Mohn, B. Keppens, K. Verhaege
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 5:532-542
A novel diode-triggered silicon-controlled rectifier (DTSCR) (Mergens et al., 2003) electrostatic discharge (ESD) protection element is introduced for low-voltage application (signal and supply voltages /spl les/ 1.8 V) with extremely narrow ESD desi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::db4b7edd86aea2a182aa6885aff4b872
https://doi.org/10.1109/tdmr.2005.853510
https://doi.org/10.1109/tdmr.2005.853510
Autor:
S. Trinh, B. Van Camp, G. Taylor, B. Keppens, K. Verhaege, Phillip Czeslaw Jozwiak, Markus Paul Josef Mergens, John Armer, Russell Mohn, Cornelius Christian Russ, F. De Ranter
Publikováno v:
Microelectronics Reliability. 43:1537-1543
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::560ed6911d0adadd6f42a36a91f1c69c
https://doi.org/10.1016/s0026-2714(03)00272-5
https://doi.org/10.1016/s0026-2714(03)00272-5
Autor:
Phillip Czeslaw Jozwiak, Markus Paul Josef Mergens, John Armer, K. Verhaege, Christian C. Russ
Publikováno v:
Microelectronics Reliability. 42:3-13
This paper presents three novel design techniques, which combined fulfill all major requirements posed on large driver and electrostatic discharge (ESD) protection transistors: minimum area consumption, good ESD robustness and optimized normal operat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::48ead063ea84bf8c28f3438eb0d515d6
https://doi.org/10.1016/s0026-2714(01)00237-2
https://doi.org/10.1016/s0026-2714(01)00237-2
Autor:
K. Verhaege, Christian C. Russ
Publikováno v:
Microelectronics Reliability. 41:1739-1749
A universal technique to design cost effective, fully silicided, high performance ESD devices is introduced [All rights reserved – Patents Pending]. This novel design solution can be implemented straightforwardly without process modifications. ESD
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f46942ed5ebbe7e78ce8f398f5a33df8
https://doi.org/10.1016/s0026-2714(01)00030-0
https://doi.org/10.1016/s0026-2714(01)00030-0
Publikováno v:
IEEE Transactions on Electronics Packaging Manufacturing. 24:99-108
This paper describes a constant impedance transmission line pulse system with new measurement capabilities and improved accuracy. The paper enforces a broader look at transmission line pulse (TLP) data, beyond the I-V curves. Accurate TLP measurement
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6bb7001694d491b7b43c8c2ef9408593
https://doi.org/10.1109/6104.930960
https://doi.org/10.1109/6104.930960
Autor:
K. Verhaege
Publikováno v:
Microelectronics Reliability. 38:115-128
This paper reviews different aspects of ESD component level testing. Traditional and alternate test methods are addressed. Focus topics are the device-under-test to tester interaction, the tester specifications and parasitics, the test procedures and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::59707dc9597c6d11cd9b8194dfa55516
https://doi.org/10.1016/s0026-2714(97)00068-1
https://doi.org/10.1016/s0026-2714(97)00068-1
Autor:
Guido Groeseneken, K. Verhaege, Karlheinz Bock, Philippe Roussel, Herman Maes, Christian Russ
Publikováno v:
Journal of Electrostatics. 42:351-381
The parasitic bipolar transistor inherent to grounded gate nMOS transistors is modelled, accounting for the specific conditions applied by CDM ESD stress. The avalanching of both, drain and source, the triggering of snapback and the CDM-specific bipo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d5d8aa79ae576079ab9dbda1dcca2b51
https://doi.org/10.1016/s0304-3886(97)00162-9
https://doi.org/10.1016/s0304-3886(97)00162-9
Publikováno v:
Microelectronics Reliability. 36:1739-1742
The parasitic bipolar transistor inherent to grounded gate nMOSts is modelled accounting for the specific conditions applied by CDM ESD stress. The impact of the gate length on the CDM-specific bipolar saturation mode is addressed. The different oper
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c26bab41f48c09fe19be1a2eb188e5fd
https://doi.org/10.1016/0026-2714(96)00187-4
https://doi.org/10.1016/0026-2714(96)00187-4
Autor:
C. Russ, F. De Ranter, K. Verhaege, Geert Wybo, B. Keppens, Markus Paul Josef Mergens, B. Van Camp, John Armer, Phillip Czeslaw Jozwiak
Publikováno v:
ISCAS (2)
This paper presents a protection strategy for ultra-sensitive I/O containing thin gate oxides, while combining two complementary ESD design approaches: (1) low-voltage diode-chain triggered SCR clamps that allow for efficient voltage clamping; (2) ac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::71258b6a321975f6a3ddf8ea9335f373
https://doi.org/10.1109/iscas.2005.1464807
https://doi.org/10.1109/iscas.2005.1464807