Zobrazeno 1 - 10
of 36
pro vyhledávání: '"K. Stawiasz"'
Autor:
Herschel A. Ainspan, John D. Crow, Young H. Kwark, Dennis L. Rogers, K. Stawiasz, D.M. Kuchta, J. Choi
Publikováno v:
Optical Fiber Communications, OFC..
Many applications for optical interconnection either require more data rate than serial links offer or are architected for parallel line (data bus) implementations. Essential to low-cost optical bus implementations are monolithic arrays of photo-rece
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4d4d4345ffaec0b8b9a5e6875148224f
https://doi.org/10.1109/ofc.1996.908318
https://doi.org/10.1109/ofc.1996.908318
Publikováno v:
2nd International Conference on ASIC.
This paper presents a low-power high-speed 10-bit D/A converter. The chip is implemented in a 0.45-/spl mu/m ASIC CMOS technology and active chip area is 0.8 mm by 0.4 mm. Its dc DNL (differential nonlinearity) is within 0.53 LSB. The chip dissipates
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4ddcf800e9db7f7ec5966aefc6fa59e3
https://doi.org/10.1109/icasic.1996.562800
https://doi.org/10.1109/icasic.1996.562800
Autor:
Peter Hong Xiao, Petar Pepeljugoski, John D. Crow, Jeannine M. Trewhella, Dianne L. Lacey, T.L. Smith, S. Tremblay, W. Nation, S.A. Igl, Stephen Louis Spanoudis, A.J. Piekarczyk, Glen Walden Johnson, B.A. DeBaun, Joong-ho Choi, Marco Gauvin, Sylvain Ouimet, S. Ponnapalli, D. Booth, M.S. Cohen, K. Stawiasz, A.S. Kuczma, G.D. Henson, D.M. Kuchta, N.A. Lee, A. Lacerte
Publikováno v:
1996 Proceedings 46th Electronic Components and Technology Conference.
The Jitney Parallel Optical Interconnect consists of a transmitter module, a receiver module, and a cable capable of sending 1 GigaByte/sec over 1-100 meter spans. This technology has been developed to be cost competitive with copper bus technology,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::57787b5d6627e9e426e195e58f00c6fa
https://doi.org/10.1109/ectc.1996.517405
https://doi.org/10.1109/ectc.1996.517405
Autor:
K. Stawiasz, Terry Marta, Robert A. Morgan, R.A. Walterson, E. Kalweit, M. Fishteyn, D.J. Muehlner, David Robert Engebretsen, Petar Pepeljugoski, Mary K. Hibbs-Brenner, Joong-ho Choi, B.K. Whitlock, P.J. Anthony, W. Nation, J.V. Gates, C.C. Faudskar, John D. Crow, John A. Lehman, Yiu-Man Wong, G.J. Cyr, D.M. Kuchta
Publikováno v:
1996 Proceedings 46th Electronic Components and Technology Conference.
This paper discusses the present state of the art of components, systems, and application technology related to parallel optical data links (ODL) as demonstrated by the OptoElectronic Technology Consortium (OETC). Parallel ODL technology is poised fo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::177423ff802ee212654c3cf082835621
https://doi.org/10.1109/ectc.1996.517403
https://doi.org/10.1109/ectc.1996.517403
Publikováno v:
1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).
System area networks (SAN) for clustered computer system architecture allow flexible growth with lower cost. SANs require high-interconnect bandwidth and long interframe distances and smaller cable bulk. Copper wire technology is beginning to show li
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::688ab5d4d9d0bd33d82b3cce4361f183
https://doi.org/10.1109/isscc.1998.672437
https://doi.org/10.1109/isscc.1998.672437
Autor:
M. Immediato, K. Stawiasz, David F. Heidel, Peter Hofstee, Kevin J. Nowka, Sang Hoo Dhong, Joel Abraham Silberman
Publikováno v:
VTS
As microprocessor speeds approach 1 GHz and beyond the difficulties of at-speed testing continue to increase. In particular, automated test equipment which operates at these frequencies is very limited. This paper discusses a design-for-test method w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1474d474feb5e880470bb9e6fe7c40e2
https://doi.org/10.1109/vtest.1998.670873
https://doi.org/10.1109/vtest.1998.670873
Autor:
Stephen V. Kosonocky, B. Parker, S. Basavaiah, David F. Heidel, R. Joshi, S. Asaad, A. Bright, K. Stawiasz, T.V. Rajeevakumar, R.A. Haring, B. Havreluk, K. Warren, S. Klepner, K. Jenkin, M. Immediato
Publikováno v:
VTS
A "system on a chip" is described, which integrates 16 Mbits of DRAM, digital logic, SRAM, three PLLs, and a triple video digital-to-analog converter in a 0.5 micron CMOS DRAM process. Application specific integrated circuit (ASIC) techniques are emp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9a2d2c716f0b9da3d4cc587ed2351387
https://doi.org/10.1109/vtest.1998.670841
https://doi.org/10.1109/vtest.1998.670841
Publikováno v:
1997 Proceedings 47th Electronic Components and Technology Conference.
The need for low cost, parallel optical bus modules that are competitively priced with existing copper bus technology necessarily implies a need for low cost testing methodologies. The testing of parallel optical bus components however poses unique c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2f485f30042b9a1ac98adfba77cd46e9
https://doi.org/10.1109/ectc.1997.606172
https://doi.org/10.1109/ectc.1997.606172
Publikováno v:
1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.
For the ever-increasing demand of communication bandwidth for clustered computer interconnections, parallel optical bus technology provides a small, lightweight, flexible and low-cost alternative to the existing technology. A 20-channel, 500 Mb/s/cha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::93b08dca76a43facd81e70393a2d4f5c
https://doi.org/10.1109/isscc.1997.585375
https://doi.org/10.1109/isscc.1997.585375
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