Zobrazeno 1 - 10
of 194
pro vyhledávání: '"K. Phoa"'
Autor:
Wesley K. Phoa
Publikováno v:
The Journal of Portfolio Management. 49:45-63
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3e404242b070fb848fe23886b2a9c169
https://doi.org/10.3905/jpm.2023.1.465
https://doi.org/10.3905/jpm.2023.1.465
Publikováno v:
The Journal of Portfolio Management. 48:258-275
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3afdb82d714dbb5b6761ea06fdbab9a4
https://doi.org/10.3905/jpm.2022.1.419
https://doi.org/10.3905/jpm.2022.1.419
Autor:
Vijaya B. Neeli, Said Rami, K. Phoa, Surej Ravikumar, Sell Bernhard, H.-J. Lee, Yuegang Zhang
Publikováno v:
2018 IEEE International Electron Devices Meeting (IEDM).
Intel 22FFL is a unique FinFET process technology optimized for RF and mmWave applications supporting superior RF performance to planar technologies with both $\boldsymbol{f_{t}}$ and $\boldsymbol{f_{max}}$ of NMOS above 300 GHz and 450 GHz respectiv
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ec3da40ea4a134cb1c96acb2b7191eec
https://doi.org/10.1109/iedm.2018.8614490
https://doi.org/10.1109/iedm.2018.8614490
Autor:
Lei Jiang, Mark Armstrong, K. W. Park, Inanc Meric, J. Standfest, C. D. Landon, Sell Bernhard, S. Liu, Ketul B. Sutaria, K. Phoa, David Young, C.-Y. Su, J. Wan, L. Paulson, S. A. Kumar, S. Ramey
Publikováno v:
IRPS
This paper describes the transistor reliability of Intel's 22FFL FinFET technology, which includes an extensive variety of device offerings to enable high performance and low power design options. Detailed evaluations of BTI, TDDB, self-heating, and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6e92475c423b4613c1c5bbd9612327d3
https://doi.org/10.1109/irps.2018.8353652
https://doi.org/10.1109/irps.2018.8353652
Autor:
Zhanping Chen, W. Xu, A. Sultana, Sell Bernhard, Ayan Kar, Nikola Stojanovic, Ranjith Kumar, Jingyan Zhang, R. Russell, M. Giraud-Carrier, J. Sandford, J. Stoeger, K. Phoa, Lajoie Travis W, Guannan Liu, S. Liu, Yuegang Zhang, S. Cha, S. Mudanai, Yunzhe Ma, Dale Young, P. Dhage, L. Paulson, P. Bai, L. Nguyen, J. Wan, Ku Chieh-Jen, H.-J. Lee, B. Bigwood, A. S. Roy, Eric Karl, James Waldemer, Pengyu Fan, K. Pierce
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
A FinFET technology named 22FFL has been developed that combines high-performance, ultra-low power logic and RF transistors as well as single-pattern backend flow for the first time. High performance transistors exhibit 57%/87% higher NMOS/PMOS drive
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::14ac3235b60c3edc9353cb96a4a26bb7
https://doi.org/10.1109/iedm.2017.8268475
https://doi.org/10.1109/iedm.2017.8268475
Autor:
J. Lee, P. Bai, T. Leo, S. K.-Y. Shi, P. Vandervoorn, D. Ingerly, L. Rockford, Ramaswamy Rahul, Y.-W. Chen, Nidhi Nidhi, F. Al-Amoody, M. Jang, K. Byon, T. Rana, Curtis Tsai, A. Zainuddin, C. Quincy, Eric Karl, L. Yang, Hafez Walid M, Chetan Prasad, C. Petersburg, Olac-Vaw Roman W, K. Komeyli, A. Kumar, Chang Hsu-Yu, Anand Subramaniam, N. L. Dias, Tsung-Yuan Chang, H. Kilambi, K. Phoa, Pei-Chi Liu, Chen-Guan Lee, C.-H. Jan
Publikováno v:
VLSIC
A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology [5] has been optimized for density, low power and wide dynamic range. 70 nm gate pitch, 52 nm metal pitch and 0.0499 um2 HDC SRAM cells are the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3ad023e07edda7779db811903bcb46fb
https://doi.org/10.1109/vlsic.2015.7231380
https://doi.org/10.1109/vlsic.2015.7231380
Autor:
Bruce Woolery, Abdur Rahman, J.-Y. Yeh, P. Bai, M. Jamil, K. Phoa, C.-H. Jan, Curtis Tsai, G. Curello, J. Hicks, M. S. Rahman, Joodong Park
Publikováno v:
2013 IEEE International Reliability Physics Symposium (IRPS).
Transistor reliability characterization studies are reported for a state of the art 22nm 3-D tri-gate HK/MG SoC technology with logic and HV I/O transistor architecture. TDDB, BTI and HCI degradation modes for logic and I/O transistors are studied an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9fd0814444461441fe012d7275e86cfe
https://doi.org/10.1109/irps.2013.6532105
https://doi.org/10.1109/irps.2013.6532105
Autor:
Abdur Rahman, J.-Y. Yeh, M. Agostinelli, K. Phoa, G. Curello, P. Bai, Joodong Park, Curtis Tsai, Hafez Walid M, C.-H. Jan, K. Komeyli, H. Deshpande, J. Xu
Publikováno v:
2011 International Reliability Physics Symposium.
Extensive reliability characterization of a state of the art 32nm strained HK/MG SoC technology with triple transistor architecture is presented here. BTI, HCI and TDDB degradation modes on the Logic and I/O (1.2V, 1.8V and 3.3V tolerant) transistors
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7ad3ffc66cc85e2e246a975e7733e28e
https://doi.org/10.1109/irps.2011.5784531
https://doi.org/10.1109/irps.2011.5784531
Autor:
Mohammed A El-Tanani, H. Deshpande, Krishnamurthy Soumyanath, S. Mudanai, Abdur Rahman, Hafez Walid M, M. Agostinelli, Hasnain Lakdawala, U. Jalan, J.-Y. Yeh, L. Rockford, Stewart S. Taylor, Kwang-Jin Koh, P. Vandervoorn, L. Janbay, H. Tashiro, L. Yang, S.-J. Choi, M. Kang, P. Bai, Curtis Tsai, J. Lin, Jad B. Rizk, K. Phoa, Hongtao Xu, J. Xu, K. Komeyli, Nick Lindert, J. Yip, G. Sacks, Ian A. Young, C.-H. Jan, G. Curello, Joodong Park
Publikováno v:
2010 Symposium on VLSI Technology.
A 32nm RF SOC technology is developed with high-k/metal-gate triple-transistor architecture simultaneously offering devices with high performance and very low leakage to address advanced RF/mobile communications markets. A high performance NMOS achie
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1b6b5e40107c1a394af62bae286b1d46
https://doi.org/10.1109/vlsit.2010.5556201
https://doi.org/10.1109/vlsit.2010.5556201
Autor:
J.-Y. Yeh, M. Prince, L. Rockford, Kevin Zhang, J. Lin, Pramod Kolar, B. Landau, H. Tashiro, Ian R. Post, Seung Hwan Lee, N. Lazo, A. Schmitz, S. Gannavaram, P. Bai, P. Vandervoorn, Zhanping Chen, S. Ma, J. Xu, G. Curello, K. Komeyli, L. Yang, Nick Lindert, J. Rizk, C.-H. Jan, S.-J. Choi, J. Yip, Yuegang Zhang, M. Agostinelli, Joodong Park, Curtis Tsai, Hafez Walid M, A. Lake, K. Phoa, N. Pradhan, H. Deshpande, C. Meining, M. Kang, L. McGill, A. Paliwal, G. Sacks, T. Leo, M. Buehler, U. Jalan, Abdur Rahman
Publikováno v:
2009 IEEE International Electron Devices Meeting (IEDM).
A leading edge 32nm high-k/metal gate transistor technology has been optimized for SoC platform applications that span a wide range of power, performance, and feature space. This technology has been developed to be modular, offering mix-and-match tra
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::93c5c78a71e8bd1f995efb0a3568b699
https://doi.org/10.1109/iedm.2009.5424258
https://doi.org/10.1109/iedm.2009.5424258