Zobrazeno 1 - 10
of 14
pro vyhledávání: '"K. Pagiamtzis"'
Autor:
Ali Sheikholeslami, K. Pagiamtzis
Publikováno v:
IEEE Journal of Solid-State Circuits. 41:712-727
We survey recent developments in the design of large-capacity content-addressable memory (CAM). A CAM is a memory that implements the lookup-table function in a single clock cycle using dedicated comparison circuitry. CAMs are especially popular in n
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ccf8dd720c567421b730481d611aad9f
https://doi.org/10.1109/jssc.2005.864128
https://doi.org/10.1109/jssc.2005.864128
Autor:
K. Pagiamtzis, Ali Sheikholeslami
Publikováno v:
IEEE Journal of Solid-State Circuits. 39:1512-1519
This paper presents two techniques to reduce power consumption in content-addressable memories (CAMs). The first technique is to pipeline the search operation by breaking the match-lines into several segments. Since most stored words fail to match in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::effd9b6e0dd120eaea811a0bbe9aa954
https://doi.org/10.1109/jssc.2004.831433
https://doi.org/10.1109/jssc.2004.831433
Publikováno v:
CICC
Modern integrated circuits require careful attention to the soft-error rate (SER) resulting from bit upsets, which are normally caused by alpha particle or neutron hits. These events, also referred to as single-event upsets (SEUs), will become more p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::01b206d95cfdc088e6c0a65288132f52
https://doi.org/10.1109/cicc.2006.320887
https://doi.org/10.1109/cicc.2006.320887
Autor:
Ali Sheikholeslami, K. Pagiamtzis
Publikováno v:
CICC
We propose using caching to save power in content-addressable memories (CAMs). By using a small cache along with the CAM, we avoid accessing the larger and higher power CAM. For a cache hit rate of 90%, the cache-CAM (C-CAM) saves 80% power over a co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::28ea94449a98cb885eedf7dead8fa88e
https://doi.org/10.1109/cicc.2005.1568682
https://doi.org/10.1109/cicc.2005.1568682
Publikováno v:
ISMVL
This paper presents four-valued magnetoresistive RAM (MRAM) storage cells using one access transistor and two binary magnetic tunnel junction (MTJ) devices, with the MTJ devices either in series or in parallel. We present a comparative study of the t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::102726ca165acf1c872e42cd344b9ef5
https://doi.org/10.1109/ismvl.2004.1319965
https://doi.org/10.1109/ismvl.2004.1319965
Autor:
K. Pagiamtzis, Ali Sheikholeslami
Publikováno v:
CICC
This paper presents a pipelined match-line and a hierarchical search-line architecture to reduce power in content-addressable memories (CAM). The overall power reduction is 60%, with 29% contributed by the pipelined match-lines and 31% contributed by
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ffc6a5d234509b833697cb6c45c2eb46
https://doi.org/10.1109/cicc.2003.1249423
https://doi.org/10.1109/cicc.2003.1249423
Autor:
P.G. Gulak, K. Pagiamtzis
Publikováno v:
The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..
Quick and accurate prediction of area, speed, and power of IP cores for SoC implementations reduces the design time and thus the overall cost. Accurate performance estimation early in the design cycle also is valuable for identifying trade-offs in th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7d1255ffab77e0c23bf0a8fcc401cf04
https://doi.org/10.1109/mwscas.2002.1187288
https://doi.org/10.1109/mwscas.2002.1187288
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