Dual Lens Electron Holography, Scanning Capacitance Microscopy (SCM), Scanning Spreading Resistance Microscopy (SSRM) Comparison for Semiconductor 2-D Junction Characterization

Autor: K. Nummy, W. Zhao, J. Nxumalo, Yun-Yu Wang, K. Bandy

Publikováno v: Microscopy Today. 29:36-44

2-D junction characterization by dual lens electron holography, scanning capacitance microscopy (SCM), and scanning spreading resistance microscopy (SSRM) on a variety of semiconductor devices is reported, including optical modulators, regular comple

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::3251800303e70876e4304e295dfc05c9
https://doi.org/10.1017/s1551929521000675

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ULSI Quality Silicon Epitaxial Growth at 850°C

Autor: K. Nummy, V. J. Silvestri, R. Bendernagel, J. Hann, V. T. Phan, D. Kerr, J. O. Borland, P. Ronsheim

Publikováno v: Journal of The Electrochemical Society. 137:2323-2327

ULSI quality silicon epitaxial films as thin as 0.6 μm have been grown using dichlorosilane at temperatures as low as 850 o C and pressures as low as 10 torr in commercially available cylindrical epi reactors. Removal of the substrate surface native

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b3c6b97bd51aa803c305b22af27c1766
https://doi.org/10.1149/1.2086935

Stress dependence and poly-pitch scaling characteristics of (110) PMOS drive current

Autor: D. Schepis, C.Y. Sung, H. Yin, B. Kim, B. Yang, M. Khare, L. Black, C. D. Sheraw, Donggun Park, H.V. Meer, X. Chen, J. Johnson, Andrew Waite, K. Nummy, H. Gossmann, P. Agnello, Philip A. Fisher, Scott Luning, S. Narasimha, D. Chidambarrao, Judson R. Holt, S. D. Kim, D. Wehella-gamage, Y. Liu

Publikováno v: 2007 IEEE Symposium on VLSI Technology.

This work demonstrates that the ~2times mobility advantage of (110) PMOS over (100) PMOS is maintained down to 190 nm liners poly-pitch for devices under compressive stress. (110) PMOS with 3.5 GPa compressively stressed liners demonstrate strong cha

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::32302cf3b5b7573ebb1e823ddd71acea
https://doi.org/10.1109/vlsit.2007.4339753

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

Autor: P. Agnello, T. Ivers, C. Warm, R. Wise, R. Wachnik, D. Schepis, S. Sankaran, J. Norum, S. Luning, Y. Li, M. Khare, A. Grill, D. Edelstein, X. Chen, D. Brown, R. Augur, S. Wu, J. Yu, R.C. Wong, J. Werking, D. Wehella-Gamage, A. Vayshenker, H. Van Meer, R. Van Den Nieuwenhuizen, C. Tian, K. Tabakman, C.Y. Sung, T. Standaert, A. Simon, J. Sim, C. Sheraw, D. Restaino, W. Rausch, R. Pal, C. Prindle, X. Ouyang, C. Ouyang, V. Ontalus, K. Nummy, D. Nielsen, L. Nicholson, A. McKnight, N. Lustig, X. Liu, M.H. Lee, D. Lea, G. Larosa, W. Landers, B. Kim, M. Kelling, S.-J. Jeng, J. Holt, M. Hargrove, S. Grunow, S. Greco, S. Gates, A. Frye, P. Fisher, A. Domenicucci, C. Dimitrakopoulos, G. Costrini, A. Chou, J. Cheng, S. Butt, L. Black, M. Belyansky, I. Ahsan, T. Adam, A. Gabor, C.-H.J. Wu, D. Yang, M. Crouse, C. Robinson, D. Corliss, C. Fonseca, J. Johnson, M. Weybright, A. Waite, H.M. Nayfeh, K. Onishi, S. Narasimha

Publikováno v: 2006 International Electron Devices Meeting.

We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniq

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::bf10344b83d49f15325667340363c388
https://doi.org/10.1109/iedm.2006.346879