Zobrazeno 1 - 10
of 108
pro vyhledávání: '"K. Maeguchi"'
Autor:
K. Maeguchi
Publikováno v:
Journal of Photopolymer Science and Technology. 7:417-422
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ba4fbfc1047eb1c885522158c61cecd9
https://doi.org/10.2494/photopolymer.7.417
https://doi.org/10.2494/photopolymer.7.417
Akademický článek
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Publikováno v:
IEEE Transactions on Electron Devices. 39:33-40
A low-temperature-processed (800-850 degrees C) bipolar transistor design suitable for the high-performance 0.5- mu m BiCMOS process is discussed. It has been found that insufficient activation of arsenic in the emitter, enhanced boron diffusion in t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d65a6868ff77bfe24a792756307b1e85
https://doi.org/10.1109/16.108209
https://doi.org/10.1109/16.108209
Autor:
Yoshiaki Toyoshima, K. Maeguchi, Kazuhiko Hashimoto, M. Nagamatsu, J. Mori, M. Hirano, M. Noda, S. Tanaka, H. Hayashida
Publikováno v:
IEEE Journal of Solid-State Circuits. 26:600-606
A 54 b*54 b multiplier fabricated in a double-metal 0.5 mu m CMOS technology is described. The 54 b*54 b full array is adopted to complete multiplication within one latency. A 10 ns multiplication time is achieved by optimizing both the propagation t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::850b58b5f61b726011e123527843df29
https://doi.org/10.1109/4.75061
https://doi.org/10.1109/4.75061
Autor:
S. Takatsuka, Yasuro Shobatake, S. Kitaoka, Kenji Sakaue, Masahiko Motoyama, Hiroyuki Hara, M. Noda, Hiroshi Momose, M. Norishima, K. Maeguchi, Shoichi Shimizu, M. Ishibe, K. Matsuda, Y. Niitsu, S. Tanaka, Y. Kumaki, T. Kodama
Publikováno v:
IEEE Journal of Solid-State Circuits. 26:1133-1144
An experimental element switch LSI for asynchronous transfer mode (ATM) switching systems was realized using 0.8- mu m BiCMOS technology. The element switch transfers cells asynchronously when used in a buffered banyan network. Three key features of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2e5eae8e7887f0c35383853b8bd84483
https://doi.org/10.1109/4.90074
https://doi.org/10.1109/4.90074
Autor:
K. Maeguchi, Hiroyuki Hara, F. Sano, S. Kobayashi, Katsuhiro Seta, Hiroshi Momose, Yohji Watanabe, M. Noda, Tetsu Nagamatsu, Y. Niitsu, Takayasu Sakurai, Hiroyuki Miyakawa
Publikováno v:
IEEE Journal of Solid-State Circuits. 26:1615-1620
A channelless gate array has been realized using 0.5- mu m BiCMOS technology integrating more than two million transistors on a 14-mm*14.4-mm chip. A small-size PMOS transistor and a small-size inverter are added to the conventional BiNMOS gate to fo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e790724c8662536cedaa9c110b567dcf
https://doi.org/10.1109/4.98980
https://doi.org/10.1109/4.98980
Publikováno v:
IEEE Transactions on Nuclear Science. 37:2089-2096
A radiation-hardened CMOS sea-of-gates technology with 1.0- mu m geometry is developed which is fully compatible with commercial technologies. Total-dose and postirradiation effects are investigated in detail on transistors and circuits designed on a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a866373a990ea724e7c497b1518c2c7d
https://doi.org/10.1109/23.101232
https://doi.org/10.1109/23.101232
Publikováno v:
IEEE Transactions on Electron Devices. 37:1487-1495
Hot-carrier-induced degradation surface-channel (p/sup +/ polysilicon gate) and buried-channel (n/sup +/ polysilicon gate) pMOSFETs is discussed. In the shallow gate bias region, a hot-carrier degradation mode by drain avalanche hot hole injection wa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dd694988d59d12e2a959a6d0ed98a6cf
https://doi.org/10.1109/16.106244
https://doi.org/10.1109/16.106244
Autor:
H. Hayashida, K. Maeguchi, Fumiyoshi Matsuoka, Hiroshi Iwai, Yoshiaki Toyoshima, Koichi Kanzaki
Publikováno v:
IEEE Transactions on Electron Devices. 37:1496-1503
The analysis indicates that a thinner gate oxide nMOSFET shows smaller degradation. Mechanisms for the smaller degradation were analyzed using a simple degraded MOSFET model. It was found that the number of the generated interface states is defined u
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8f1807af6876e0296c63c9d674b9f880
https://doi.org/10.1109/16.106245
https://doi.org/10.1109/16.106245
Autor:
Fumiyoshi Matsuoka, Koichi Kanzaki, K. Maeguchi, Hiroshi Iwai, H. Itoh, T. Nakakubo, K. Hama, R. Nakata
Publikováno v:
IEEE Transactions on Electron Devices. 37:562-568
Experiments have shown that the electromigration reliability for conventional nonfilled via holes decreases with via hole diameter reduction. Tungsten-filled via hole reliability, however, is independent of the via hole diameter and improves signific
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eb97d6432f6cb420e6d1e3b3d52d91ec
https://doi.org/10.1109/16.47758
https://doi.org/10.1109/16.47758