Zobrazeno 1 - 10
of 22
pro vyhledávání: '"K. Komeyli"'
Autor:
J. Lee, P. Bai, T. Leo, S. K.-Y. Shi, P. Vandervoorn, D. Ingerly, L. Rockford, Ramaswamy Rahul, Y.-W. Chen, Nidhi Nidhi, F. Al-Amoody, M. Jang, K. Byon, T. Rana, Curtis Tsai, A. Zainuddin, C. Quincy, Eric Karl, L. Yang, Hafez Walid M, Chetan Prasad, C. Petersburg, Olac-Vaw Roman W, K. Komeyli, A. Kumar, Chang Hsu-Yu, Anand Subramaniam, N. L. Dias, Tsung-Yuan Chang, H. Kilambi, K. Phoa, Pei-Chi Liu, Chen-Guan Lee, C.-H. Jan
Publikováno v:
VLSIC
A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology [5] has been optimized for density, low power and wide dynamic range. 70 nm gate pitch, 52 nm metal pitch and 0.0499 um2 HDC SRAM cells are the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3ad023e07edda7779db811903bcb46fb
https://doi.org/10.1109/vlsic.2015.7231380
https://doi.org/10.1109/vlsic.2015.7231380
Autor:
K. Komeyli, H. Tashiro, J.-Y. Yeh, Joodong Park, C. Staus, M. Kang, M. Jang, Uddalak Bhattacharya, P. Bai, Abdur Rahman, Chia-Hong Jan, Kinyip Phoa, Curtis Tsai, P. Vandervoorn, Ruth A. Brain, L. Yang, G. Curello, Nidhi Nidhi, S.-J. Choi, G. Gupta, Hafez Walid M, L. Pan, T. Leo
Publikováno v:
2012 International Electron Devices Meeting.
A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, < 65mV/dec subthreshold slope and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::65cbc6de11013a48dd62c1a5522bbbc4
https://doi.org/10.1109/iedm.2012.6478969
https://doi.org/10.1109/iedm.2012.6478969
Autor:
Abdur Rahman, J.-Y. Yeh, M. Agostinelli, K. Phoa, G. Curello, P. Bai, Joodong Park, Curtis Tsai, Hafez Walid M, C.-H. Jan, K. Komeyli, H. Deshpande, J. Xu
Publikováno v:
2011 International Reliability Physics Symposium.
Extensive reliability characterization of a state of the art 32nm strained HK/MG SoC technology with triple transistor architecture is presented here. BTI, HCI and TDDB degradation modes on the Logic and I/O (1.2V, 1.8V and 3.3V tolerant) transistors
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7ad3ffc66cc85e2e246a975e7733e28e
https://doi.org/10.1109/irps.2011.5784531
https://doi.org/10.1109/irps.2011.5784531
Autor:
Mohammed A El-Tanani, H. Deshpande, Krishnamurthy Soumyanath, S. Mudanai, Abdur Rahman, Hafez Walid M, M. Agostinelli, Hasnain Lakdawala, U. Jalan, J.-Y. Yeh, L. Rockford, Stewart S. Taylor, Kwang-Jin Koh, P. Vandervoorn, L. Janbay, H. Tashiro, L. Yang, S.-J. Choi, M. Kang, P. Bai, Curtis Tsai, J. Lin, Jad B. Rizk, K. Phoa, Hongtao Xu, J. Xu, K. Komeyli, Nick Lindert, J. Yip, G. Sacks, Ian A. Young, C.-H. Jan, G. Curello, Joodong Park
Publikováno v:
2010 Symposium on VLSI Technology.
A 32nm RF SOC technology is developed with high-k/metal-gate triple-transistor architecture simultaneously offering devices with high performance and very low leakage to address advanced RF/mobile communications markets. A high performance NMOS achie
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1b6b5e40107c1a394af62bae286b1d46
https://doi.org/10.1109/vlsit.2010.5556201
https://doi.org/10.1109/vlsit.2010.5556201
Autor:
Ian R. Post, Hafez Walid M, Kaizad Mistry, K. Komeyli, Curtis Tsai, P. Bai, Chetan Prasad, J. Hicks, M. Jones, Roza Kotlyar, C.-H. Jan, J. Lin, S. Gannavaram
Publikováno v:
2010 IEEE International Reliability Physics Symposium.
In this paper, we present extensive reliability characterization results for a novel dual gate 45nm HK+MG technology. BTI, HCI and TDDB degradation modes on the Logic and I/O transistors are studied and excellent reliability is demonstrated. Emphasis
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f391925a4e2a22a0aaddc59bef3388ee
https://doi.org/10.1109/irps.2010.5488815
https://doi.org/10.1109/irps.2010.5488815
Autor:
J.-Y. Yeh, M. Prince, L. Rockford, Kevin Zhang, J. Lin, Pramod Kolar, B. Landau, H. Tashiro, Ian R. Post, Seung Hwan Lee, N. Lazo, A. Schmitz, S. Gannavaram, P. Bai, P. Vandervoorn, Zhanping Chen, S. Ma, J. Xu, G. Curello, K. Komeyli, L. Yang, Nick Lindert, J. Rizk, C.-H. Jan, S.-J. Choi, J. Yip, Yuegang Zhang, M. Agostinelli, Joodong Park, Curtis Tsai, Hafez Walid M, A. Lake, K. Phoa, N. Pradhan, H. Deshpande, C. Meining, M. Kang, L. McGill, A. Paliwal, G. Sacks, T. Leo, M. Buehler, U. Jalan, Abdur Rahman
Publikováno v:
2009 IEEE International Electron Devices Meeting (IEDM).
A leading edge 32nm high-k/metal gate transistor technology has been optimized for SoC platform applications that span a wide range of power, performance, and feature space. This technology has been developed to be modular, offering mix-and-match tra
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::93c5c78a71e8bd1f995efb0a3568b699
https://doi.org/10.1109/iedm.2009.5424258
https://doi.org/10.1109/iedm.2009.5424258
Autor:
C. Litteken, C.-H. Jan, Hafez Walid M, J. Yip, Zhanping Chen, K. Komeyli, J. Rizk, N. Lazo, J.-Y. Yeh, N. Pradhan, C. Tsai, Rachael J. Parker, M. Kang, Kaizad Mistry, Yih Wang, Ian R. Post, Chetan Prasad, L. Yang, Nick Lindert, S. Olson, Jun He, M. Jones, L. Pei, J. Hicks, S. Naskar, D. Towner, J. Lin, P. Bai, S. Gannavaram, M. Prince, G. Sacks, G. Curello, Joodong Park, M. Buehler, H. Tashiro, U. Jalan, A. Mezhiba, S. Biswas
Publikováno v:
2008 IEEE International Electron Devices Meeting.
A leading edge 45 nm CMOS system-on-chip (SOC) technology using Hafnium-based high-k/metal gate transistors has been optimized for low power products. PMOS/NMOS logic transistor drive currents of 0.86/1.08 mA/um, respectively, have been achieved at 1
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::650637eed7ee1291376a576974fdaa08
https://doi.org/10.1109/iedm.2008.4796772
https://doi.org/10.1109/iedm.2008.4796772
Autor:
G. Curello, K. Komeyli, Nick Lindert, J. Rizk, G. Sacks, S. Gannavaram, P. Bai, J. Lin, C.-H. Jan, D. Yeh, Joodong Park, Ian R. Post, U. Jalan, C. Tsai, Muhammad Akbar, Hafez Walid M
Publikováno v:
2006 International Electron Devices Meeting.
Record breaking RF performance was recently achieved on a 65nm CMOS technology (29nm Lgate, 210nm pitch) employing uni-axial strained silicon transistors. These highest-reported cutoff frequencies for NMOS transistors achieve fT/fMAX values of 360 GH
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c651ea657b290d7d8a502d4261783987
https://doi.org/10.1109/iedm.2006.346816
https://doi.org/10.1109/iedm.2006.346816
Publikováno v:
International Symposium for Testing and Failure Analysis.
SRAM bit fail maps (BFM) are routinely collected during earlier phases of yield ramping, providing a rich source of information for IC failure and deformation learning. In this paper, we present an automated approach to analyzing BFM data efficiently
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8c05e8b1afa1424c858f3313e476179d
https://doi.org/10.31399/asm.cp.istfa2003p0232
https://doi.org/10.31399/asm.cp.istfa2003p0232
Publikováno v:
VTS
Previously published work has pointed out that open defects are escaping test screens. To plug this hole, tests directed at nets susceptible to opens are required, and, therefore, nets susceptible to opens need to be identified. Opens caused by rando
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2d17ff437a2c02dc2bdc5789f03e3eeb
https://doi.org/10.1109/vts.2002.1011166
https://doi.org/10.1109/vts.2002.1011166