Zobrazeno 1 - 10
of 12
pro vyhledávání: '"K. Kanebako"'
Autor:
Khandker N. Quader, Dhritiman Ghosh, Hidehiro Shiga, Tapan Samaddar, M. Watanabe, Jonathan Huynh, Patrick Hong, Hiroshi Maejima, Norihiro Fujita, Jongmin Park, Mototsugu Hamada, Trung Pham, Gyuwan Kwon, James Chan, Grishma Shah, D. Pantelakis, Sharon Huynh, T. Kaneko, Debi Das, Liping Peng, Qui Nguyen, Calvin Chia-Hong Kuo, Byungki Woo, Man L. Mui, Chi-Ming Wang, Hao Thai Nguyen, Masaaki Higashitani, Ray Gao, Eugene Tam, K. Kanebako, Khin Htoo, Tien-chien Kuo, Yupin Fong, Yan Li, V. Kalluru, A. Koh, Sanjay Kulkarni, Seungpil Lee, Cernea Raul Adrian, Ken Oowada, P. Kliza, Iris Lu, Jun Wan, James Lan, Emilio Yero, Feng Pan, Hardwell Chibvongodze, Teruhiko Kamei
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:195-207
A 16 Gb 8-level NAND flash chip on 56 nm CMOS technology has been fabricated and is being reported for the first time. This is the first 3-bit per cell (X3) chip published with all-bitline (ABL) architecture, which doubles the write performance compa
Autor:
Mitsuaki Honma, S. Hoshi, Mark Murin, T. Shimizu, T. Kawaai, Michio Nakagawa, K. Nagaba, K. Kanebako, K. Kanazawa, Y. Komatsu, Arik Eyal, Hiroshi Maejima, K. Imamiya, H. Tabata, Menahem Lasser, K. Iwasa, T. Shano, M. Kosakai, Mark Shlick, Noboru Shibata, Masaki Fujiu, Hiroto Nakai, A. Inoue, Katsuaki Isobe, S. Yoshikawa, Avraham Meir, T. Takahashi, N. Motohashi
Publikováno v:
IEEE Journal of Solid-State Circuits. 43:929-937
A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed . This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash, and quadruple bit density
Autor:
K. Kanebako, N. Matsukawa
Publikováno v:
Microelectronic Engineering. 48:121-124
This paper provide a new model for TDDB lifetime distribution based on statistical considerations. The model is based on two assumptions: an assumption of hole capture cross section and an assumption of critical defect number. In this model, a small
Autor:
C. Trinh, N. Shibata, T. Nakano, M. Ogawa, J. Sato, Y. Takeyama, K. Isobe, B. Le, F. Moogat, N. Mokhlesi, K. Kozakai, P. Hong, T. Kamei, K. Iwasa, J. Nakai, T. Shimizu, M. Honma, S. Sakai, T. Kawaai, S. Hoshi, J. Yuh, C. Hsu, T. Tseng, J. Li, J. Hu, M. Liu, S. Khalid, J. Chen, M. Watanabe, H. Lin, J. Yang, K. McKay, K. Nguyen, T. Pham, Y. Matsuda, K. Nakamura, K. Kanebako, S. Yoshikawa, W. Igarashi, A. Inoue, T. Takahashi, Y. Komatsu, C. Suzuki, K. Kanazawa, M. Higashitani, S. Lee, T. Murai, J. Lan, S. Huynh, M. Murin, M. Shlick, M. Lasser, R. Cernea, M. Mofidi, K. Schuegraf, K. Quader
Publikováno v:
ISSCC
Today NAND Flash memory is used for data and code storage in digital cameras, USB devices, cell phones, camcorders, and solid-state disk drives. Figure 13.6.1 shows the memory-density trend since 2003. To satisfy the market demand for lower cost per
Autor:
Jonathan Huynh, S. Kulkarni, Byungki Woo, Hiroshi Maejima, P. Kliza, M. Watanabe, T. Kaneko, Chi-Ming Wang, D. Ghosh, James Chan, Tien-chien Kuo, Yan Li, J. Lan, Tapan Samaddar, I. Lu, Hitoshi Shiga, Ray Gao, Norihiro Fujita, Feng Pan, Ken Oowada, Grishma Shah, Raul-Adrian Cernea, Khin Htoo, Jong Park, Qui Nguyen, Seungpil Lee, Gyuwan Kwon, M. Higashitani, Hardwell Chibvongodze, V. Kalluru, C. Kuo, D.K. Das, E. Tarn, Teruhiko Kamei, Emilio Yero, P. Hong, M. Hamada, K. Quader, Liping Peng, A. Koh, Jun Wan, D. Pantelakis, Trung Pham, Man Mui, Yupin Fong, Hao Nguyen, S. Huynh, K. Kanebako
Publikováno v:
ISSCC
We present an 8 MB/s 3-bit per cell (D3) NAND flash memory that uses the same number of ECC bytes as 2-bit per cell (D2) NAND. Since no extra columns are added in D3 devices, the 16 Gb D3 chip in this paper achieves 0.112 Gb/mm2 compared to 0.079 Gb/
Autor:
T. Shano, K. Kanebako, M. Kosakai, Y. Komatsu, S. Yoshikawa, Masaki Fujiu, Michio Nakagawa, A. Inoue, K. Iwasa, T. Takahashi, H. Tabata, Katsuaki Isobe, S. Hoshi, Hiroto Nakai, K. Kanazawa, Noboru Shibata, N. Motohashi, T. Shimizu, Mitsuaki Honma, Kenichi Imamiya, Hiroshi Maejima, K. Nagaba, T. Kawaai
Publikováno v:
2007 IEEE Symposium on VLSI Circuits.
A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed. This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash with the same design rule. N
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