Zobrazeno 1 - 10
of 24
pro vyhledávání: '"K. Heragu"'
Autor:
V. Gupta, Yiqun Xie, L. Dyson, R. Gu, Paul E. Landman, Bhavesh G. Bhakta, John Powers, W. Mohammed, Ah-Lyan Yee, K. Heragu, Wai Lee, Lin Wu, Mustafa Ulvi Erdogan, B. Parthasarathy, Keith Brouse, Robert Floyd Payne, Song Wu, Srinath Ramaswamy
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:2646-2657
A transceiver capable of 6.25-Gb/s data transmission across legacy communications equipment backplanes is described. To achieve a bit error rate (BER)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2447560f09f9be5f8da0f41cb5ece132
https://doi.org/10.1109/jssc.2005.856583
https://doi.org/10.1109/jssc.2005.856583
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 21:1502-1508
Dynamic logic is increasingly becoming a logic type of choice for designs requiring high speed and low area. Charge sharing is one of many problems that may cause failure in dynamic logic circuits due to their low noise immunity. The authors address
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::87a2d65f0795090b7f4f23a700eccab9
https://doi.org/10.1109/tcad.2002.804377
https://doi.org/10.1109/tcad.2002.804377
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 16:759-762
A recently proposed method obtains path delay fault coverages by estimating the count of the number of tested faults instead of actually enumerating them. The estimate becomes pessimistic when several paths share a set of lines. In this communication
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::29742dab99cda526cb070c16915baa47
https://doi.org/10.1109/43.644037
https://doi.org/10.1109/43.644037
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 14:590-596
We have developed a new statistical technique for estimating delay fault coverage in combinational circuits. True value simulation is performed for a sample of vector pairs chosen randomly from the test set. Transition probabilities and observabiliti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dd95ff0a58460b0adb5431fd73e8dfc0
https://doi.org/10.1109/43.384421
https://doi.org/10.1109/43.384421
Autor:
Robert Floyd Payne, Bhavesh G. Bhakta, Ulvi Erdogan, Ah-Lyan Yee, Srinath Ramaswamy, L. Dyson, John Powers, B. Parthasarathy, Yiqun Xie, Lin Wu, Song Wu, R. Gu, Keith Brouse, W. Mohammed, Paul E. Landman, K. Heragu, Wai Lee, V. Gupta
Publikováno v:
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
A transmit architecture with a programmable 4-tap feedforward equalizer for 6.25 to 12.5 Gb/s serial communications through lossy channels is described. A 16:8-channel MUX/DEMUX chip fabricated in a 0.13 /spl mu/m 7M CMOS process demonstrates a near-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::15a38b7aef36a2961232cbd0ce92f5fd
https://doi.org/10.1109/isscc.2005.1493871
https://doi.org/10.1109/isscc.2005.1493871
Autor:
Keith Brouse, W. Mohammed, Bhavesh G. Bhakta, Ah-Lyan Yee, Song Wu, V. Gupta, B. Parthasarathy, Yiqun Xie, Srinath Ramaswamy, Paul E. Landman, Ulvi Erdogan, L. Dyson, Wai Lee, R. Gu, K. Heragu, John Powers, Robert Floyd Payne, Lin Wu
Publikováno v:
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..
A 6.25 Gb/s serial receiver with a 4-tap adaptive DFE is implemented in a 0.13 /spl mu/m 7LM CMOS process. Direct cancellation of the first post-cursor ISI is achieved, enabling recovery of a data eye fully closed from channel losses and crosstalk. A
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cb067ab133c08f8eb2cfbd2c055e3314
https://doi.org/10.1109/isscc.2005.1493872
https://doi.org/10.1109/isscc.2005.1493872
Publikováno v:
VLSI Design
A recently published method computes path delay fault coverage from the count of the number of path faults newly sensitized by a simulated vector pair. Such an estimate is pessimistic since several paths may share a set of lines. In this paper, we pr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ca279bb484707f176917d67295fceac0
https://doi.org/10.1109/icvd.1996.489646
https://doi.org/10.1109/icvd.1996.489646
Publikováno v:
Proceedings of International Conference on Computer Aided Design.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6f180eb5e829658e2f2dfac3b53080b9
https://doi.org/10.1109/iccad.1996.569902
https://doi.org/10.1109/iccad.1996.569902
Publikováno v:
VTS
We propose a new statistical technique for estimating fault coverage in combinational circuits. Our method requires fault-free simulation of a random sample of vectors from the test vector set. Fault coverage is computed from controlabilities and obs
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::01bad53162d776d28efdfcde122dbf99
https://doi.org/10.1109/vtest.1994.292302
https://doi.org/10.1109/vtest.1994.292302
Publikováno v:
VLSI Design
We have developed new statistical techniques for delay fault analysis. True value simulation is performed using a multi-value logic system describing signal states of two consecutive vectors. Signal statistics are used to estimate transition probabil
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aba40bd3362a409bd10fed37f67dd383
https://doi.org/10.1109/icvd.1995.512098
https://doi.org/10.1109/icvd.1995.512098