Zobrazeno 1 - 10
of 473
pro vyhledávání: '"K. Brayton"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41:2573-2586
This article proposes a new logic synthesis and verification paradigm based on circuit simulation. In this paradigm, high quality, expressive simulation patterns are pregenerated to be reused in multiple runs of optimization and verification algorith
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8a92e14e25ca925fc62dbc760c040607
https://doi.org/10.1109/tcad.2021.3108704
https://doi.org/10.1109/tcad.2021.3108704
Publikováno v:
DAC
The paper addresses a key aspect of efficient computation in logic synthesis and formal verification, namely, the integration of a circuit simulator and a Boolean satisfiability solver. A novel way of interfacing these is proposed along with a fast p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a6bce593b9ec8643a6add35b53df7bb2
https://doi.org/10.1109/dac18074.2021.9586331
https://doi.org/10.1109/dac18074.2021.9586331
Autor:
Kevin A. Schulman, Bipin Mistry, Robert S. Kaplan, Brent C. James, Arnold Milstein, M.C. Mazza, M. Kalani, R. Mann, V.G. Narayanan, J. Xue, Terry Platchek, C. Pinnock, J. Punnen, G. Poulsen, Christine Nguyen, Feryal Erhun, Michael J. Mack, D. Shetty, D. Ballard, K. Brayton, Dhruv S. Kazi
Publikováno v:
American Heart Journal
Background Multiple modern Indian hospitals operate at very low cost while meeting US-equivalent quality accreditation standards. Though US hospitals face intensifying pressure to lower their cost, including proposals to extend Medicare payment rates
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8a6ff749f86fbd95dba2b352d01d77eb
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35:919-930
This paper introduces ${m}$ -inductiveness over a set of nodes ${S}$ in sequential circuits. The ${m}$ -inductive property can be used for equivalence-checking or improved sequential optimization. It allows the behavior of many next state functions (
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::de41ee7116f99a414095180769e41313
https://doi.org/10.1109/tcad.2015.2481860
https://doi.org/10.1109/tcad.2015.2481860
Autor:
Fan Mo, Robert K. Brayton
Publikováno v:
EDA for IC Implementation, Circuit Design, and Process Technology ISBN: 9781315221694
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e3372e934c0bca4367ff934028b3b277
https://doi.org/10.1201/9781420007954-7
https://doi.org/10.1201/9781420007954-7
Publikováno v:
DAC
A representation of a Boolean function is canonical if, given a variable order, only one instance of the representation is possible for the function. A computation is canonical if the result depends only on the Boolean function and a variable order,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2dd5d8267ae644d6f7cf5afe9dbffcc1
https://doi.org/10.1145/3195970.3196006
https://doi.org/10.1145/3195970.3196006
Autor:
Luca Amaru, Mathias Soeken, Winston Haaswijk, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli, Eleonora Testa
Publikováno v:
DATE
In this paper, we discuss recent advances in exact synthesis, considering both their efficient implementation and various applications in which they can he employed. We emphasize on solving exact synthesis through Boolean satisfiability (SAT) encodin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1e45207f353c192729dc1eff5bb9aeb5
https://doi.org/10.23919/date.2018.8342027
https://doi.org/10.23919/date.2018.8342027
Publikováno v:
Proceedings of the IEEE. 103:1952-1957
The articles in this special issue provides an overview of and a perspective on the evolution of electronic design automation (EDA), and offers a perspective on some of the principal avenues of future development.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::acf2bbd1a286a0709f4a455d521aa195
https://doi.org/10.1109/jproc.2015.2487798
https://doi.org/10.1109/jproc.2015.2487798
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 33:305-317
Sequential logic synthesis often leads to substantially easier equivalence checking problems, compared to general-case sequential equivalence checking (SEC). This paper theoretically investigates when SEC can be reduced to a combinational equivalence
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9b12794658312fb5fb87459112f38b83
https://doi.org/10.1109/tcad.2013.2284190
https://doi.org/10.1109/tcad.2013.2284190