Zobrazeno 1 - 5
of 5
pro vyhledávání: '"K V Kumaraswamy"'
Publikováno v:
2018 4th International Conference for Convergence in Technology (I2CT).
This paper signifies the transient analysis of the PLL and is implemented in cadence tool using 180nm technology node. Frequency is expected to be in GHz range for present communication systems to increase the speed and therefore PLL is designed to p
Publikováno v:
2018 4th International Conference for Convergence in Technology (I2CT).
One of most popular algorithm of cryptography is AES, which has data block of 16bytes and key size is variable of 128bits, 192bits and 256bits. In proposed design, AES method implemented by the use of Verilog using Xilinx ISE 14.7, which reduces oper
Publikováno v:
2016 International Conference on Emerging Technological Trends (ICETT).
Implementation of filter needs mainly three basic building blocks as multiplier, adder and signal delay. If a filter has to be speed means it should have high speed basic building block i.e. multiplier and adder blocks should be very high speed. The
Publikováno v:
2016 International Conference on Emerging Technological Trends (ICETT).
This paper shows the working of an I2C protocol for multiple masters-multiple slave configuration operation. When multiple masters are considered, it is necessary to know which master has got the bus. To know this, Arbitration technique has been impl
Publikováno v:
2016 International Conference on Emerging Technological Trends (ICETT).
Digital Signal Processing has become popular these days because of development of data converters with high resolution and high speed. Analog to Digital Converter (ADC) and Digital to Analog Converter (DAC) are integral part of Digital Communication