Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Jyunichi Suyama"'
Autor:
Jyunichi Suyama, Daisuke Kitayama, Miyuki Akazawa, Hiroshi Kudo, Yumi Okazaki, Tanaka Masaya, Ryohei Kasai, Kouji Sakamoto, Haruo Iida, Satoru Kuramochi, Shouhei Yamada, Yuuki Aritsuka, Mitsuhiro Takeda, Takamasa Takano, Hiroaki Sato
Publikováno v:
2018 International Conference on Electronics Packaging and iMAPS All Asia Conference (ICEP-IAAC).
The fabrication of a 2.5D glass interposer was demonstrated, and its electrical performance, including signal transmission, was characterized. Single-sided multi-level enhanced copper redistribution layers were fabricated on a glass substrate with th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a2a5d68846411db9edf5be51d9cd6970
https://doi.org/10.23919/icep.2018.8374332
https://doi.org/10.23919/icep.2018.8374332
Autor:
Daisuke Kitayama, Hiroshi Kudo, Jyunichi Suyama, Shouhei Yamada, Satoru Kuramochi, Miyuki Akazawa, Kouji Sakamoto, Ryohei Kasai, Yumi Okazaki, Hiroaki Sato, Mitsuhiro Takeda, Haruo Iida
Publikováno v:
2017 IEEE CPMT Symposium Japan (ICSJ).
Downsizing the Cu signal traces in the redistribution layer is an effective approach to increasing the number of signal I/O lines and thereby greatly increasing signal processing performance between logic and memory chips in advanced fine-pitch packa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2afd95dcab8f482bad22764ac26a0628
https://doi.org/10.1109/icsj.2017.8240055
https://doi.org/10.1109/icsj.2017.8240055
Autor:
Daisuke Kitayama, Yumi Okazaki, Ryohei Kasai, Kouji Sakamoto, Shouhei Yamada, Jyunichi Suyama, Toshio Sasao, Satoru Kuramochi, Hiroaki Sato, Haruo Iida, Hiroshi Kudo, Mitsuhiro Takeda
Publikováno v:
2017 IEEE 67th Electronic Components and Technology Conference (ECTC).
Aggressive scaling down of the Cu trace pitch in the redistribution layer (RDL) is needed to meet the design rule for high-density I/O used in advanced packaging. Such a downsized RDL, however, will be vulnerable to voltage and current stresses, in a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7d951762a00d24c7fbba6f9bc177bf8b
https://doi.org/10.1109/ectc.2017.8
https://doi.org/10.1109/ectc.2017.8
Autor:
Daisuke Kitayama, Miyuki Akazawa, Hiroyuki Sato, Masaya Tanaka, Kouji Sakamoto, Hiroshi Mawatari, Yumi Okazaki, Ryohhei Kasai, Hiroshi Kudo, Shouhei Yamada, Toshio Sasao, Susumu Tashiro, Naoki Oota, Satoru Kuramochi, Haruo Iida, Takamasa Takano, Mitsuhiro Takeda, Jyunichi Suyama
Publikováno v:
2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
An enhanced redistribution layer architecture has been developed in which the Cu wires are directly covered with a double layer consisting of two types of dielectrics by using a semi-additive process. The double layer enhanced the thermal and electri
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c989cb81643fa8b51aa38b80758c324b
https://doi.org/10.1109/ectc.2016.69
https://doi.org/10.1109/ectc.2016.69