Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Jyu-Horng Shieh"'
Autor:
C.H. Lin, C.Y. Ting, M.S. Liang, J.W. Hsu, Jyu-Horng Shieh, Y.N. Su, J.S. Tsai, S.M. Jang, C.L. Chou
Publikováno v:
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
This paper investigated various approaches to integrate Cu and extra low-k dielectric (ELK, k=2.5~2.2) for dual damascene fabrication. We demonstrate a trench-first hard mask process flow without k degradation by ash-free process and a novel pore sea
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5ecb18e7375740317a169762f0e3aa4e
https://doi.org/10.1109/iedm.2005.1609273
https://doi.org/10.1109/iedm.2005.1609273
Autor:
Ming-Yong Lee, Tang-Hsuan Chung, Chien-Chao Huang, Chang-Yun Chang, Tzyh-Cheang Lee, Tsung-Lin Lee, Ju-Wang Hsu, Ji-Hua Wang, Baw-Ching Perng, Jyu-Horng Shieh, Jiunn-Ren Hwang, Fu-Liang Yang, Huan-Chi Ma, Chih-Yuan Ting, Sheng-Da Liu
Publikováno v:
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
High-performance FinFET SONOS (silicon-oxide-nitride-oxide-silicon) flash cells with gate length down to 20nm have been fabricated and operated successfully on bulk-silicon substrate for the first time. A program/erase window of 2V has been achieved
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::232e0464f488d93e89d71e8da3384c26
https://doi.org/10.1109/iedm.2005.1609293
https://doi.org/10.1109/iedm.2005.1609293
Autor:
Baw-Ching Perng, Renee Huang, M.S. Liang, S.M. Jang, Li-Chien Chen, Ruey-Lian Hwang, Joe Hsu, David Fong, Jyu-Horng Shieh
Publikováno v:
SPIE Proceedings.
The need for absolute accuracy is increasing as semiconductor-manufacturing technologies advance to sub-65nm nodes, since device sizes are reducing to sub-50nm but offsets ranging from 5nm to 20nm are often encountered. While TEM is well-recognized a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d69fc2d16d25849bcab9dc3538b2b7f1
https://doi.org/10.1117/12.655986
https://doi.org/10.1117/12.655986
Autor:
Huang Peter Yu-Fei, Fang-Cheng Chen, Ryan C. J. Chen, S.M. Jang, M.S. Liang, Baw-Ching Perng, Jyu-Horng Shieh
Publikováno v:
SPIE Proceedings.
Scatterometry is gaining popularity in recent years as it shows itself as a worthy contender among existing metrology systems. Scatterometry provides fast, accurate and precise profile information, which is valuable for in-line process control in pro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::56b82e56608e012f2868a9e3db0f2a0c
https://doi.org/10.1117/12.656226
https://doi.org/10.1117/12.656226
Publikováno v:
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..
We demonstrate a near-field scanned microwave probe and specific test keys for direct non-contact electrical measurement of low-k dielectric constant and damage after deposition, during trench/via processing, and after metallization. This work succes
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::baeef91a30b5c1a7072a08a5e07f4a4d
https://doi.org/10.1109/vlsit.2006.1705242
https://doi.org/10.1109/vlsit.2006.1705242
Autor:
J.S. Tsai, Jyu-Horng Shieh, R.L. Hwang, M.C. Liang, M.S. Liang, J.J. Lee, T.L. Lee, S.M. Jang, L.C. Cher
Publikováno v:
2006 International Interconnect Technology Conference.
We demonstrate that after a fine-tuned ashing process the damage behavior of extra low-k material (ELK, k=2.5) is continued at the surface and the thickness of the damaged layer can be kept under control. Therefore, damaged-free treatment can be achi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2d4841ea7d3dc60bf34af395fd64a5c6
https://doi.org/10.1109/iitc.2006.1648650
https://doi.org/10.1109/iitc.2006.1648650
Publikováno v:
Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..
This work investigates the leakage and breakdown mechanisms in a Cu damascene structure with carbon-doped CVD extra low-k material (ELK, k=2.5) as intermetal dielectric. The effects of ash processing by inductively coupled plasma (ICP) and reactive i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a55df49d49d92a13b56e56c638611e2b
https://doi.org/10.1109/iitc.2005.1499937
https://doi.org/10.1109/iitc.2005.1499937
Novel 20nm hybrid SOI/bulk CMOS technology with 0.183μm/sup 2/ 6T-SRAM cell by immersion lithography
Autor:
null Hou-Yu Chen, null Chang-Yun Chang, null Chien-Chao Huang, null Tang-Xuan Chung, null Sheng-Da Liu, null Jiunn-Ren Hwang, null Yi-Hsuan Liu, null Yu-Jun Chou, null Hong-Jang Wu, null King-Chang Shu, null Chung-Kan Huang, null Jan-Wen You, null Jaw-Jung Shin, null Chun-Kuang Chen, null Chia-Hui Lin, null Ju-Wang Hsu, null Bao-Chin Perng, null Pang-Yen Tsai, null Chi-Chun Chen, null Jyu-Horng Shieh, null Han-Jan Tao, null Shih-Chang Chen, null Tsai-Sheng Gau, null Fu-Liang Yang
Publikováno v:
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
For the first time, a novel hybrid SOI/bulk CMOS technology with 20nm gate length and low-leakage 1.3nm thick SiON gate dielectric has been developed for advanced SOC applications. 26% (for N-FET) and 35% (for P-FET) improvements of intrinsic gate de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2b6438477da572f34e824ad8a96c84a7
https://doi.org/10.1109/.2005.1469194
https://doi.org/10.1109/.2005.1469194
Autor:
R.Y. Huang, Jang-Jung Lee, Jyu-Horng Shieh, S.M. Jang, M.-S. Liang, H.Y. Chu, Y.N. Su, J.M. Chiou, C.Y. Ting, J.S. Tsai
Publikováno v:
ISSM 2005, IEEE International Symposium on Semiconductor Manufacturing, 2005..
STEM-EDS analysis on the sidewall surface of ultra low-k dielectric (ULK), a CVD SiOC type low-k dielectric (k /spl ap/ 2.5), has been performed to study the damage behavior of low-k material during strip. Carbon depletion was observed on the sidewal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c64a28a13fc7dc58feac0b6124d0eb2e
https://doi.org/10.1109/issm.2005.1513330
https://doi.org/10.1109/issm.2005.1513330
Autor:
Chien-Chao Huang, Jyu-Horng Shieh, Jam-Wem Lee, Hou-Yu Chen, Hung-Wei Chen, Chang-Yun Chang, Chi-Chun Chen, Chenming Hu, Tang-Xuan Chung, Shih-Chang Chen, Yee-Chia Yeo, Di-Hong Lee, Cheng-Chuan Huang, Fu-Liang Yang, C.H. Chen, Yiming Li, Pu Chen, Mong-Song Liang, Han-Jan Tao, Peng-Fu Hsu, C.C. Wu, Ying-Tsung Chen, Yi-Hsuan Liu, Bor-Wen Chan, Ying-Ho Chen, Sheng-Da Liu
Publikováno v:
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..
A new nanowire FinFET structure is developed for CMOS device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and 10 nm physical gate length, respectively, are fabricated. N-FET gate delay (CV/I) of 0.22 p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1fb47840b46cc559f0c572d8e1e9a16f
https://doi.org/10.1109/vlsit.2004.1345476
https://doi.org/10.1109/vlsit.2004.1345476