Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Jyh-Rong Lin"'
Publikováno v:
Microelectronics Reliability. 52:916-921
In this paper, we have developed and revealed the wafer-level LED system-in-packaging (WL-LED-SiP) design and process platform. This platform provided an LED system solution with high packaging density, high performance, high reliability and cost eff
Autor:
Jyh-Rong Lin, Raymond S. T. Lee
Publikováno v:
IEEE Transactions on Systems, Man and Cybernetics, Part B (Cybernetics). 31:413-417
In this paper, an elastic graph dynamic link model (EGDLM) based on elastic contour matching is proposed to automate the Dvorak technique for tropical cyclone (TC) pattern interpretation from satellite images. This method integrates traditional dynam
Publikováno v:
2009 Asia Pacific Microwave Conference.
We present a thin film on modified ceramic (TFoMC) technique in this work to achieve high-accuracy and high-uniformity design. The integrated passive devices (IPDs), including capacitors, inductors, band-pass filters and Baluns, are realized based on
Publikováno v:
2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS).
We have developed a thin-film on modified ceramic (TFoMC) technology in this work to achieve high-density, high-accuracy and high-uniformity substrate technology for RF-related applications. Integrated passive devices (IPDs), including capacitors, in
Publikováno v:
2009 4th International Microsystems, Packaging, Assembly and Circuits Technology Conference.
In this paper, we have developed a Thin Film on Modified Ceramic (TFoMC) technology which provides not only a low-cost but also high-performance solution, especially for wireless local-area network (WLAN) related applications. To begin with, a warpag
Publikováno v:
Proceedings Electronic Components and Technology, 2005. ECTC '05..
For several kinds of advanced applications, such as RFID, telecommunication, portable electronics, or wearable electronics, the need of packaged semiconductor chip thick is getting thinner drastically. One representative technology is to embed an act
Autor:
Tzu-Ying Kuo, Yu-Hua Chen, Jyh-Rong Lin, A. Neumann, Shou-Lung Chen, A. Ostmann, Cheng-Ta Ko, Chien-Wei Chien, Shan-Pu Yu
Publikováno v:
Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971).
The structure of chip-in-substrate package, CiSP, is shown. The thin chips (50mum) are bonded on the organic substrate (BT) flatly. Subsequently, the chips are covered among the build-up dielectric layer, which can be either a RCC (resin coated coppe
Autor:
Jyh-Rong Lin, Yu-Jiau Hwang, Hsu-Tien Hu, Yu-Chih Chen, Ruoh-Huey Uang, Kuo-Chuan Chen, Shu-Ming Chang
Publikováno v:
4th Electronics Packaging Technology Conference, 2002..
Recently, flip chip package has obtained more and more attentions due to its benefits of high I/O, low inductance and better thermal dissipation. Therefore flip chip package is getting to be used in some high performance and high speed devices such a
Autor:
Kuo-Chuan Chen, Jyh-Rong Lin, Shu-Ming Chang, Wei-Chung Lo, Yu-Chih Chen, Hsu-Tien Hu, Yu-Jiau Hwang, Li-Cheng Shen
Publikováno v:
4th Electronics Packaging Technology Conference, 2002..
In this paper, one of the wafer level chip scale packaging (WL-CSP) patents issued by ERSO/ITRI, the double elastomer wafer level package, is implemented on the test vehicle of Rambus DRAM to demonstrate the applicability and reliability of WL-CSP fo
Publikováno v:
2010 Proceedings 60th Electronic Components & Technology Conference (ECTC); 2010, p1568-1574, 7p