Zobrazeno 1 - 10 of 149 pro vyhledávání: '"Jwu-E CHEN"'
1
Akademický článek
Retesting Schemes That Improve Test Quality and Yield Using a Test Guardband
Autor: Chung-Huang Yeh, Jwu-E Chen
Publikováno v: Eng, Vol 4, Iss 4, Pp 3007-3025 (2023)
The digital integrated circuit (IC) testing model module is applied in this study to simulate the fabrication and testing of integrated circuits. The yield and quality of ICs are analyzed by assuming that the wafer devices under test conditions are n
Externí odkaz: https://doaj.org/article/bba3669b01974c72a6084f2bb2ff5b3f
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2
Akademický článek
Application of Three-Repetition Tests Scheme to Improve Integrated Circuits Test Quality to Near-Zero Defect
Autor: Chung-Huang Yeh, Jwu-E Chen
Publikováno v: Sensors, Vol 22, Iss 11, p 4158 (2022)
In this research, the normal distribution is assumed to be the product characteristic, and the DITM (Digital Integrated Circuit Test Model) model is used to evaluate the integrated circuits (IC) test yield and test quality. Testing technology lags fa
Externí odkaz: https://doaj.org/article/f7b10b14325e4c6db44b792705e6d425
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7
Machine Learning-Based Detection Method for Wafer Test Induced Defects
Autor: Nova Cheng-Yen Tsai, Katherine Shu-Min Li, Leon Chou, Ji-Wei Li, Leon Li-Yang Chen, Andrew Yi-Ann Huang, Hsing-Chung Liang, Jwu E. Chen, Chen-Shiun Lee, Chun-Lung Hsu, Sying-Jyan Wang, Ken Chau-Cheung Cheng
Publikováno v: IEEE Transactions on Semiconductor Manufacturing. 34:161-167
Wafer test is carried out after integrated circuits (IC) fabrication to screen out bad dies. In addition, the results can be used to identify problems in the fabrication process and improve manufacturing yield. However, the wafer test itself may indu
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::cdb6a20e453a616bf09e0e03effcfdf9
https://doi.org/10.1109/tsm.2021.3065405
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8
Hidden Wafer Scratch Defects Projection for Diagnosis and Quality Enhancement
Autor: Hsin-Chung Liang, Ken Chau-Cheung Cheng, Leon Li-Yang Chen, Andrew Yi-Ann Huang, Peter Yi-Yu Liao, Chung-Lung Hsu, Gus Chang-Hung Han, Sying-Jyan Wang, Katherine Shu-Min Li, Jwu E. Chen, Leon Chou
Publikováno v: IEEE Transactions on Semiconductor Manufacturing. 34:9-16
Wafer map defect pattern recognition provides useful clues to yield learning. However, most wafer maps have no special spatial patterns and are full of noises, which make pattern recognition difficult. Especially, recognizing scratch and line types o
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c036514f5013e7f23d91f7130f9c20e3
https://doi.org/10.1109/tsm.2020.3040998
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9
Test yield and quality analysis models of chips
Autor: Chung Huang Yeh, Jwu E. Chen
Publikováno v: Journal of the Chinese Institute of Engineers. 43:279-287
In this work, we utilized a digital integrated-circuit (IC) testing model (DITM), based on a statistical simulation method, to evaluate the test yield and test quality of semiconductor prod...
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::fb0b939fbc21acfe49c463214094f6ad
https://doi.org/10.1080/02533839.2019.1708806
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10
Using Enhanced Test Systems Based on Digital IC Test Model for the Improvement of Test Yield
Autor: Chung-Huang Yeh, Jwu-E Chen, Chia-Jui Chang, Tse-Chia Huang
Publikováno v: Electronics; Volume 11; Issue 7; Pages: 1115
In this work, we use statistical concepts to evaluate the joint probability distribution of manufacturing and test parameters and estimate the future trend of wafer test yield. Owing to the difference between the development speeds of testing technol
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::53f0b11e02777432eb31f3d9e7a071b7
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