Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Junran Pu"'
Autor:
Liwei Yang, Huaipeng Zhang, Tao Luo, Chuping Qu, Myat Thu Linn Aung, Yingnan Cui, Jun Zhou, Ming Ming Wong, Junran Pu, Anh Tuan Do, Rick Siow Mong Goh, Weng Fai Wong
Publikováno v:
Neurocomputing. 474:128-140
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f04e59d26521f1b84bcbc7c4db9d7a2b
https://doi.org/10.1016/j.neucom.2021.12.021
https://doi.org/10.1016/j.neucom.2021.12.021
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 68:5081-5094
In recent years, fast computation, low power, and small footprint are the key motivations for building SNN hardware. The unique features of SNN hardware have not been fully exploited, where the computation speed and energy efficiency of the SNN hardw
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::beb6a68c9df719a22262a0a7c5d85938
https://doi.org/10.1109/tcsi.2021.3112979
https://doi.org/10.1109/tcsi.2021.3112979
Autor:
Fei Li, Wang Ling Goh, Yun Kwan Lee, Junran Pu, Anh Tuan Do, Aarthy Mani, Eng Kiat Koh, Vishnu P. Nambiar, Ming Ming Wong
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 68:3148-3152
This brief presents a neuromorphic processor with asynchronous routers and configurable LIF neuron models. The neurocore microarchitecture revolves around a high- $V_{th}$ SRAM to reduce leakage, alongside reconfigurable neuron compute logic circuits
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f064a2e9790a37ea4707e01aed7d3719
https://doi.org/10.1109/tcsii.2021.3096883
https://doi.org/10.1109/tcsii.2021.3096883
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 68:1398-1402
With the ability to generate different spiking patterns, Izhikevich model has well been considered a computationally efficient and biologically plausible neuron model for applications such as brain dynamic behavior study. This brief presents a low-co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::706e479d0a15bbf2d057616d70baa8bf
https://doi.org/10.1109/tcsii.2020.3023825
https://doi.org/10.1109/tcsii.2020.3023825
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 68:471-475
Neuromorphic (NC) designs have gained significant interest in recent hardware research due to its low-power consumption. Low-power and low-latency router design is one of the most critical component to ensure NC hardware’s scalability and energy ef
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::331a980ee858866c5f831767a50adafb
https://doi.org/10.1109/tcsii.2020.3005725
https://doi.org/10.1109/tcsii.2020.3005725
Autor:
Liwei Yang, Huaipeng Zhang, Tao Luo, Chuping Qu, Myat Thu Linn Aung, Yingnan Cui, Jun Zhou, Ming Ming Wong, Junran Pu, Anh Tuan Do, Rick Siow Mong Goh, Weng Fai Wong
Publikováno v:
Neurocomputing. 508:109
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d219fe17de065bd96795fe631c672858
https://doi.org/10.1016/j.neucom.2022.06.079
https://doi.org/10.1016/j.neucom.2022.06.079
Autor:
Fei Li, Anh Tuan Do, Eng Kiat Koh, Wang Ling Goh, Ming Ming Wong, Aarthy Mani, T. Luo, Junran Pu, Yun Kwan Lee, L. Yang, V. P. Nambiar
Publikováno v:
A-SSCC
This paper proposes a scalable neuromorphic processor utilizing asynchronous routers and configurable LIF neuron models. The routing fabric's asynchronous protocol allows for critical timing paths between blocks to be relaxed and reduces power consum
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::609b087d7897e7ae9c7e273969c92d71
https://doi.org/10.1109/a-sscc48613.2020.9336142
https://doi.org/10.1109/a-sscc48613.2020.9336142
Autor:
Wong Ming Ming, Li Fei, Junran Pu, Wang Ling Goh, Anh Tuan Do, Eng Kiat Koh, Vishnu P. Nambiar, Aarthy Mani
Publikováno v:
ISCAS
This paper proposes a scalable hardware architecture for block-based spiking neural networks utilizing a multiplierless spiking neuron model. These blocks were implemented as a neurocore mesh generated from an interconnect algorithm, allowing for sea
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dcd3d0f8a5c3e57fd85c95e13498d354
https://doi.org/10.1109/iscas45731.2020.9180629
https://doi.org/10.1109/iscas45731.2020.9180629
Publikováno v:
SoCC
Network-on-Chip has been widely used as an interconnection fabric due to its high scalability. However, traditional router designs target multiprocessor systems-on-chips, and therefore needs to be improved according to the characteristics of neuromor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f8d47c7f481d39d934bf5e4c901229f
https://doi.org/10.1109/socc46988.2019.1570548462
https://doi.org/10.1109/socc46988.2019.1570548462