Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Junhee Lim"'
Autor:
Jin-kyu Kang, Jaeduk Lee, Yongsik Yim, Sejun Park, Hyun Suk Kim, Eun Suk Cho, Taehun Kim, Jung Hoon Lee, Joon Kim, Raeyoung Lee, Junhee Lim, Sunghoi Hur, Su Jin Ahn, Jaihyuk Song
Publikováno v:
2021 IEEE International Electron Devices Meeting (IEDM).
Autor:
J. Jang, Jae-Hoon Lee, Satoru Yamada, Sungkweon Baek, Jong-Ho Lee, Jaehyun Yeo, Joon Han, Chanmin Lee, Junhee Lim, Jang Sung Ho, Kyu-Pil Lee
Publikováno v:
2019 IEEE International Electron Devices Meeting (IEDM).
A 35nm node 4Gbit LPDDR3 prototype with high-k metal gate (HKMG) peripheral transistors is implemented for the first time using processes that are fully compatible with those of conventional commercial DRAMs with poly/SiON (PSiON) transistors. This p
Autor:
Seung-Mok Shin, Taiki Uemura, E. S. Jung, Seungbae Lee, Y. Ji, Hyunjo Shin, Joo-Byoung Yoon, H. J. Goo, Yun-Jae Lee, Kyongtaek Lee, Jun-Kyun Park, S. H. Hwang, Jung Hyoung Lee, Jongkyun Kim, G. T. Jeong, Seung-Uk Han, Y. J. Song, K. C. Park, Sun-Ghil Lee, G. H. Koh, B. Y. Seo, Sangwoo Pae, Junhee Lim
Publikováno v:
IRPS
STT-MRAM has great attention as next generation memory to replace commercialized memory. However, not many articles are available on various MRAM reliability items. In this paper, we studied FBC trend of STT-MRAM with ECC off mode under various relia
Publikováno v:
2016 IEEE International Electron Devices Meeting (IEDM).
Scaling limitations in planar-NAND cell are discussed, including the depletion of floating gate and anomalous programming behavior. It is inevitable to have a paradigm shift to 3D-NAND due to numerous scaling limitations of planar NAND. However, the
Autor:
Sungho Jang, E. S. Jung, Hyeongsun Hong, Seung-Uk Han, Satoru Yamada, Sungkweon Baek, Wonchang Jeong, Kijae Huh, Sung-Sam Lee, Junhee Lim, Gyo-Young Jin, Moonyoung Jeong, Kyu-Pil Lee
Publikováno v:
2016 IEEE 8th International Memory Workshop (IMW).
An analysis on the degradation of DRAM performance caused by the NBTI degradation of p-MOSFET is first to be reported. To improve the NBTI immunity, three candidates are examined. First, minimizing Si-H bonds at Si/SiON interface through controlling
Autor:
Kinam Kim, Y.M. Kang, D.Y. Choi, H.S. Rhie, S.Y. Lee, H. J. Joo, Byoung-Jae Bae, J.H. Park, S.K. Kang, H.S. Jeong, B.J. Koo, Junhee Lim
Publikováno v:
Integrated Ferroelectrics. 81:57-67
In this study we present an MOCVD-PZT-based 1.6 V operational 1T1C COB FRAM for embedded smart card applications. The extension of FRAM operation to low voltage requires reduction of PZT thickness to 100 nm which is accompanied by a degradation of sa
Publikováno v:
Solid-State Electronics. 39:923-927
In this work, the hot carrier degradation behavior of the halo doped MOSFETs is investigated and an optimized halo design, taking into account the hot carrier reliability, is proposed. Conventional LDD MOSFETs and halo MOSFETs with the variations in
Autor:
Hyuck-Chai Jung, Tae-Young Chung, Kyungseok Oh, Junhee Lim, Sang-Woon Lee, Seok-Han Park, Kinam Kim, Won-suk Yang, Bonggu Sung, Joo-young Lee
Publikováno v:
2008 IEEE International Reliability Physics Symposium.
One of the most important issues for DRAM development is the control of data retention time. A negatively-biased off-state level of the word line (NWL) was introduced to the memory cell design to improve cell transistor "on" current and to maintain "
Autor:
S.Y. Lee, B.J. Koo, J.H. Park, H.S. Rhie, Junhee Lim, H.S. Jeong, S.K. Kang, Byoung-Jae Bae, Y.M. Kang, H. J. Joo, Kinam Kim
Publikováno v:
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
We newly developed a highly reliable 100 nm thick MOCVD PZT technology and a novel direct cell via technology applicable to fully logic compatible sub 10F/sup 2/ cell embedded FRAM. A 2Pr value of 40 uC/cm/sup 2/ at 1.6V was obtained on our one-mask
Publikováno v:
33rd IEEE International Reliability Physics Symposium.
In this work, hot carrier degradation behavior of the halo doped MOSFETs is investigated and an optimized halo design, taking into account the hot carrier reliability, is proposed. Conventional LDD MOSFETs and halo MOSFETs with the variations in LDD