Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Jungyul Pyo"'
Autor:
Youngmin Shin, Chung-hee Kim, Kim Jongwoo, Dong-Yeop Kim, Yong-geol Kim, Jungyul Pyo, Hyun Cheol Lee, Min-Su Kim, Ah-Reum Kim, Jae Cheol Son, Dae-Seong Lee
Publikováno v:
ISCAS
The paper proposes a novel practical replacement of conventional high-speed clock-gates for wide voltage scaling. The proposed clock-gate enhances the energy-delay-product by 43% and improves the low-voltage operation by 50 mV reducing the sampling w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::91cfd1bf3c5874001c6bbd673694e587
https://doi.org/10.1109/iscas.2018.8351444
https://doi.org/10.1109/iscas.2018.8351444
Publikováno v:
IEEE Communications Magazine. 51:94-98
This article introduces a 32 nm application processor designed for the latest high-performance smart handheld devices and discusses its design targets and options. To meet unprecedented levels of performance and data throughput demands, this processo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::84fb9cb3bc1fef4f3ca9d467470a23c7
https://doi.org/10.1109/mcom.2013.6495767
https://doi.org/10.1109/mcom.2013.6495767
Autor:
Ilsuk Suh, Youngmin Shin, Chung-hee Kim, Yong-geol Kim, Dae-Seong Lee, Changjun Choi, Ji-Kyum Kim, Min-Su Kim, Kang Ju-Hyun, Ah-Reum Kim, Jungyul Pyo, Jae Cheol Son
Publikováno v:
SoCC
A novel high-speed single-ended D flip-flop based on a SR(set/reset)-type latch is presented in this paper. The SR-type latch is adapted to implement a dynamic stage for high-speed operation and modified to add a scan mux without setup time degradati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2a6f85f0004111a5010fc83f78ad6f73
https://doi.org/10.1109/socc.2016.7905442
https://doi.org/10.1109/socc.2016.7905442
Autor:
Youngmin Shin, Kwang-Il Kim, Sunghee Yun, Min-Su Kim, Jae Cheol Son, Inyup Kang, Sung-il Bae, Jungyul Pyo, Hoi-Jin Lee
Publikováno v:
2015 International SoC Design Conference (ISOCC).
This paper presents a heterogeneous configuration of two 64-bit different target quad-core CPUs. To support both high-performance and high energy-efficiency depending on application requirements, two types of 64-bit quad-core CPUs are implemented in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::64c2f7b40466f80f7398cd5e2a5c5d72
https://doi.org/10.1109/isocc.2015.7401760
https://doi.org/10.1109/isocc.2015.7401760
Autor:
Min-Su Kim, Jae Cheol Son, Sung-Wook Lee, Chung-hee Kim, Hoi-Jin Lee, Sunghee Yun, Yohan Kwon, Heung-Chul Oh, Kwang-Il Kim, Uk-Rae Cho, Sungho Park, Jungyul Pyo, Inpyo Hong, Hee Soo Kim, Jin-Soo Park, Dongwook Lee, Kyungkuk Chae, Jong-Ho Lee, Jae-Young Lim, Ken Shin, Youngmin Shin, Seong-Ho Song, Heon-Hee Lee, Sung-il Bae
Publikováno v:
ISSCC
The demands for high-performance smart mobile devices are growing exponentially every year. Like the PC market, 64b CPUs are needed to meet this demand. Furthermore, mobile GPU performance is becoming increasingly important as mobile game graphics re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::85a94dc2b29fdcb5de0f80a1f966c4eb
https://doi.org/10.1109/isscc.2015.7063105
https://doi.org/10.1109/isscc.2015.7063105