Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Jung-no Im"'
Autor:
Dae-Seok Byeon, Kyung-Hwa Kang, Yongsu Choi, Jeon Hongsoo, Hyung-Gon Kim, Minseok Kim, Jeong-Don Ihm, Seon-Kyoo Lee, Kye-Hyun Kyung, Sungwhan Seo, Sung-Min Joe, Jin-Yub Lee, Su-Chang Jeon, Kitae Park, Byung-Hoon Jeong, HyunWook Park, Moosung Kim, Kim Su-Yong, Sung-Won Yun, Sangbum Yun, Young-Min Kim, Park Jiyoon, Hyang-ja Yang, Jong-Hoon Lee, Yong-Sik Yim, Sungkyu Jo, Byung-Kyu Cho, Hyejin Yim, Makoto Hirano, Jonghoon Park, Tae-eun Kim, Deok-kyun Woo, Lee Kang-Bin, Chan-Ho Kim, Hoosung Kim, Jongyeol Park, Jung-no Im, Yang-Lo Ahn, Seung-jae Lee, Jeong-Hyuk Choi, Park Il-Han, Minsu Kim, Jin-Tae Kim, Dooho Cho, Ho-Kil Lee
Publikováno v:
ISSCC
NAND flash memory is widely used as a cost-effective storage with high performance [1–2]. This paper presents a 128Gb multi-level cell (MLC) NAND flash memory with a 150 cells/string structure in 14nm CMOS that can be used as a cost-effective stora
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7b2055eff5e06a7382aaf3e142458866
https://doi.org/10.1109/isscc.2016.7417945
https://doi.org/10.1109/isscc.2016.7417945
Autor:
An-Soo Park, Ik Joon Chang, Kye Hyun Kyung, Jongyeol Park, Chi-Weon Yoon, Moosung Kim, Kyung-Min Kang, Hoosung Kim, Wook-Ghee Hahn, You-Se Kim, Young-Ho Lim, Seokjun Ham, Byung-Gil Jeon, Sung-Won Yun, Lim Bong-Soon, Ji-Sang Lee, Young-Hyun Jun, Sang-Hyun Joo, Tae-Sung Lee, Doo-gon Kim, Jung-no Im, Yongsung Cho, Sangyong Yoon, Kyungryun Kim, Byung-Jun Min, Kihwan Choi, Seunghyuk Kwon, Joon-Suc Jang, Jae-Duk Yu, Jeong-yun Yun, Jinman Han, Jin-Young Chun, Park Il-Han, Nam-hee Lee, Dong-Su Jang, Ki-whan Song, Daeyeal Lee
Publikováno v:
ISSCC
The market growth of mobile applications such as smart phones and tablet computers has fueled the explosive demand of NAND Flash memories having high density and fast throughput. To meet such a demand, we present a 64Gb multilevel cell (MLC) NAND Fla
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::907c1918b3024f80ecf45c8d034b687e
https://doi.org/10.1109/isscc.2012.6177077
https://doi.org/10.1109/isscc.2012.6177077
Publikováno v:
IEE Proceedings - Circuits, Devices and Systems. 150:45
The paper describes a differential CMOS logic family employing self-timing for speed enhancement and charge recycling for power reduction. The logic family is up to 49% faster than other types of dynamic circuits. A pseudo one-phase clocking pipeline
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::875782c1ad8a419f21dbb1e00794a192
https://doi.org/10.1049/ip-cds:20030271
https://doi.org/10.1049/ip-cds:20030271