Zobrazeno 1 - 10
of 78
pro vyhledávání: '"Jung-Suk Goo"'
Autor:
Benjamin Iniguez, Yogesh Singh Chauhan, Slobodan Mijalkovic, Kejun Xia, Jung-Suk Goo, Marcelo Pavanello, Marek Mierzwinski, Wladek Grabinski
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 8, Pp 1350-1353 (2020)
This Special Issue is dedicated to recent research in the field of compact modeling of semiconductor devices. This is the first J-EDS Special Issue on compact modeling. In the last years, a number of new semiconductor device structures, for electroni
Externí odkaz:
https://doaj.org/article/c705e340a46a41f3be623285f270f28c
Autor:
Slobodan Mijalkovic, W. Grabinski, Yogesh Singh Chauhan, Kejun Xia, Jung-Suk Goo, M. Mierzwinski, Marcelo Antonio Pavanello, Benjamin Iniguez
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 8, Pp 1350-1353 (2020)
This Special Issue is dedicated to recent research in the field of compact modeling of semiconductor devices. This is the first J-EDS Special Issue on compact modeling. In the last years, a number of new semiconductor device structures, for electroni
Autor:
Jung-Suk Goo, N. Pimparkar, Wafa Arfaoui, Robert Tu, Germain Bossu, Steffen Lehmann, A.B. Icel, Pratik B. Vyas, M. Siddabathula
Publikováno v:
IRPS
Accurate prediction of device aging plays a vital role in the circuit design of advanced-node CMOS technologies. In particular, hot-carrier induced aging is so complicated that its modeling is often significantly simplified, with focus limited to dig
Autor:
A. Mehta, S. Mahajan, Owen Hu, Kok Wai Johnny Chew, Kumaran Sundaram, Abdellatif Bellaouar, Palanivel Balasubramaniam, Jerome Ciavatti, Ram Asra, Jung-Suk Goo, Ravi M. Todi, H. S. Yang, David Harame, Jagar Singh, Abhijit Bandyopadhyay, S. Yamaguchi, Jen Shuang Wong, C. Kyono, Josef S. Watts, Shuming Li, D. K. Sohn, X. Zhang, Shesh Mani Pandey, E. Geiss, Srikanth Samavedam, Alexander L. Martin, AJ Bousquet, S. B. Mittal, Baofu Zhu
Publikováno v:
2017 Symposium on VLSI Technology.
This paper highlights a 14nm Analog and RF technology based on a logic FinFET platform for the first time. An optimized RF device layout shows excellent F t /F max of (314GHz/180GHz) and (285GHz/140GHz) for NFET and PFET respectively. A higher PFET R
Publikováno v:
Solid-State Electronics. 48:1417-1422
Transport in Si NMOSFETs with gate lengths from 48 to 23 nm is investigated by full-band Monte Carlo device simulation for three sets of devices: (I) unstrained Si control devices, (II) process matched strained Si devices, and (III) threshold voltage
Publikováno v:
IEEE Transactions on Electron Devices. 47:655-658
Accurate external resistance extraction for shallow source/drain extension (SDE) MOSFET's is demonstrated using a unified mobility model for inversion and accumulation layers. The parasitic resistance in the accumulation layer (R/sub acc/) is highly
Publikováno v:
IEEE Transactions on Electron Devices. 47:1843-1850
A reconstruction technique of the gate capacitance from anomalous capacitance-voltage (C-V) curves in high leakage dielectric MOSFETs is presented. An RC network is used to accommodate the distributed nature of MOSFETs and an optimization technique i
Autor:
Hiroshi Iwai, Francois Danneville, Robert W. Dutton, Jung-Suk Goo, Thomas H. Lee, Eiji Morifuji, Chang-Hoon Choi, Zhiping Yu, Hisayo Momose
Publikováno v:
IEEE Transactions on Electron Devices. 47:2410-2419
Based on an active transmission line concept and two-dimensional (2-D) device simulations, an accurate and computationally efficient simulation technique for high frequency noise performance of MOSFETs is demonstrated. Using a Langevin stochastic sou
Autor:
V. Pham, Chuanzhao Yu, S.K. Jayanarananan, J.S. Yuan, F. Duan, J. Zhang, A. Marathe, Jung-Suk Goo, S. Cooper
Publikováno v:
IEEE Electron Device Letters. 28:45-47
This letter evaluates a radio-frequency (RF) method to extract the gate capacitance for SOI MOSFETs with ultrathin ultraleaky gate dielectrics. Conventional methods such as two-element and three-element methods using precision impedance analyzer were
Publikováno v:
IEEE Electron Device Letters. 25:819-821
This letter demonstrates that the conventional two-element lumped model can provide valid capacitance-voltage (C-V ) characteristics for gate oxides with large tunneling current, if the gate length is reduced. The two-element models generally suffer